The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As fault-tolerant Networks-on-Chip (NoCs) become prevalent in reliable systems, their overhead must be accurately evaluated. In this paper, we evaluate the overhead of a soft error resilient real-time NoC router for ASICs in terms of area and power. We employ a power analysis framework and load profiles that provide accurate power figures. Furthermore, we analyze the power behavior in normal operation...
Conventional fault-tolerance approaches for Networks-on-Chip (NoCs) cannot be applied to high assurance real-time systems due to their different goals and constraints. These systems impose strict integrity, resilience and real-time requirements. All possible effects of hardware errors must be taken into account and the resulting system must be predictable, even in the presence of errors. In this paper,...
Networks-on-Chip (NoCs) are the backbone of Multiprocessor Systems-on-Chip (MPSoCs). In this paper, we perform a formal worst-case communication time analysis of Automatic Repeat reQuest (ARQ) protocols for NoCs. Therefor, we integrate the transport layer analysis for general networks and the network layer analysis for NoCs. An ARQ variant optimized for DMA transfers (DMA ARQ) is introduced and analyzed...
Network-on-Chip (NoC) based multi- and many-core architectures show high potential for use in real-time applications due to their superior efficiency. In real-time systems, it is necessary to guarantee that the application's timing requirements are met through the analysis of the worst-case behavior. A typical approach to guarantee real-time is the exclusive assignment of virtual channels to tasks...
Network-on-Chip-based multi- and many-core architectures show high potential for use in safety-critical real-time applications, such as Flight Management Systems, considering their superior efficiency. For such use however, safety standards require proof that the architecture meets the specified security goals. This usually involves a Failure Mode and Effects Analysis (FMEA) to reveal the effects...
Multi- and many-core architectures using Networks-on-Chip (NoC) are being explored for use in real-time safety-critical applications for their performance and efficiency. Such systems must provide isolation between tasks that may present distinct criticality levels. The NoC is critical to maintain the isolation property as it is a heavily used shared resource. To meet safety-standard requirements,...
Chip multiprocessing is key to Mobile and high-end Embedded Computing. It requires sophisticated multilevel hierarchies where private and shared caches coexist. It relies on hardware support to implicitly manage relaxed program order and write atomicity so as to provide well-defined shared-memory semantics (captured by the axioms of a memory consistency model) at the hardware-software interface. This...
Chip multiprocessing (CMP) changed the architectural landscape of PCs and servers and is now changing the way personal mobile devices are designed. CMP requires access to shared variables in private memories, leading to complex chains of interacting events that must offer a consistent view of shared memory. Checking if a memory system implements a specified memory consistency model (MCM) is a challenging...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.