The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Highly regular many-core architectures tend to be more and more popular as they are suitable for inherently highly parallelizable applications such as most of the image and video processing domain. In this article, we present a novel architecture for many-core microprocessor ASIC dedicated to embedded video and image processing applications. We propose a flexible many-core approach with two architectures...
The gap of execution time between software and hardware computing is significant and becomes more and more important when precision is required as it is the case for the floating point calculation. This paper presents the addition of a Floating Point Unit (FPU) module to an open-source processor called SecretBlaze. Besides the description of the chosen processor enhanced by FPU thanks to user instructions,...
For many image processing systems, the computing power required can not be provided by a single sequential processor, this is why many designers appeal to multiprocessor systems (parallelism). This article proposes an original flexible MP-SoC (Multi-Processors System on Chip) architecture for image processing applications. Developing processors network systems tailored to a particular application...
In many video and image processing applications, complexity has reached a point where the performance requirements can no longer be supported by standard architectures based on a single processor. This is why many systems are based on multiprocessor architecture. In this paper, we present HNCP-II a 16-core flexible distributed memory ASIC dedicated to embedded application field (image processing applications)...
Many previous works have introduced courses on necessary design steps for a basic knowledge of the digital ASIC design flow. This paper intends to introduce a series of labs focusing on ASIC design flow on a complex case study. Indeed, many difficult aspects of the ASIC flow only appear with complex design. This course enables teaching modern and industrial advanced digital ASIC design methodologies...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.