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Low duty-cycle mobile systems can benefit from ultra-low power deep neural network (DNN) accelerators. Analog in-memory computational units are used to store synaptic weights in on-chip non-volatile arrays and perform current-based calculations. In-memory computation entirely eliminates off-chip weight accesses, parallelizes operation, and amortizes readout power costs by reusing currents. The proposed...
Wearable devices have been on the mind of the semiconductor industry for several years now. The vision was of a highly sensorized human, with electronic devices providing localized, always-available functionality for a range of applications, including medical, health and wellness, lifestyle, etc. But, has this vision panned out? Is the technology there? Was there any application-level value to begin...
The Internet of Things (IoT) is a rapidly emerging application space, poised to become the largest electronics market for the semiconductor industry. IoT devices are focused on sensing and actuating of our physical environment and have a nearly unlimited breadth of uses. In this paper, we explore the IoT application space and then identify two common challenges that exist across this space: ultra-low...
We present LIT, a low power, low cost audio processor for information dissemination to and among illiterate people in developing regions. The 265K gate, 8 million transistor, 23mm2, ARM Cortex M0 processor uses a novel memory hierarchy consisting of an on chip 128kB true LRU cache and off-chip flash. It is designed for efficient operation on Carbon Zinc batteries and has a high-level of integration...
A 128 kb portless SRAM is presented with 1024 rows per hierarchical bitline and CMOS thyristor-based local sense amplifiers. Each portless cell is 0.317 μm2 in 45 nm CMOS and consumes 50.8 fJ of energy per access at a 17.86 ns cycle time. A 65% read SNM improvement and a 33% leakage power reduction is achieved over a conventional 6T design. The thyristor-based sense amplifier occupies 2.4 μm2 and...
Recent work in ultra-low-power sensor platforms has enabled a number of new applications in medical, infrastructure, and environmental monitoring. Due to their limited energy storage volume, these sensors operate with long idle times and ultra-low standby power ranging from 10s of nW down to 100s of pW. Since radio transmission is relatively expensive, even at the lowest reported power of 0.2mW, wireless...
In this paper, the authors also show how clocking overhead can be reduced through circuit techniques to facilitate super pipelining while process variation is addressed through the use of latch-based design. Additionally, architecture modifications are proposed to improve energy efficiency and throughput. Measurements show that the FFT core consumes 17.7nJ per 1024-pt complex FFT while operating at...
Glaucoma is the leading cause of blindness, affecting 67 million people worldwide. The disease damages the optic nerve due to elevated intraocular pressure (IOP) and can cause complete vision loss if untreated. IOP is commonly assessed using a single tonometric measurement, which provides a limited view since IOP fluctuates with circadian rhythms and physical activity. Continuous measurement can be...
We propose an adaptive reliability enhancement structure for deeply-scaled CMOS and future devices that exhibit nondeterministic behavior. This structure forms the basis of a confidence-driven computing model that can be implemented in either a rollback recovery or an iterative dual modular redundancy method incorporating synchronous handshake schemes. The performance and cost of the computing model...
Driven by continued scaling of Moore's Law, the number of processing elements on a die are increasing dramatically. Recently there has been a surge of wide single instruction multiple data architectures designed to handle computationally intensive applications like 3D graphics, high definition video, image processing, and wireless communication. A limit of the SIMD width of these types of architectures...
Increase in variability in the nanometer era has contributed to pessimistic guardbands for conventional circuit design techniques that optimize at worst-case process corners. Smart deterministic approaches have been proposed that employ statistical timing analysis to reduce pessimism in the guardbands while retaining the deterministic nature of the algorithms. Other statistical optimization techniques...
Double patterning lithography (DPL) is widely considered the only lithography solution for 32nm and several subsequent technology nodes. DPL decomposes and prints the critical layout shapes in two exposures, leading to mismatch between adjacent devices due to systematic offsets between the two exposures. This results in adjacent devices with different mean critical dimension (CD), and uncorrelated...
Bell's Law predicts continual reductions in the size of computing systems. We investigate the status of the next paradigm shift that will usher in ubiquitous computing - sub-mm3 sensor nodes. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to battery size. This paper describes new ultra-low power circuit techniques applied to digital processors,...
A digitally trimmable voltage reference is proposed, achieving a tight distribution of temperature coefficient and output voltage, along with pA-range current consumption for Vdd=0.5-3.0V. Using 2 temperature point digital trimming, the temperature coefficient and nominal output voltage are within 5.3-47.4ppm/°C and 175.2-176.5mV across 25 dies in 0.13μm CMOS. Non-trimmable versions are also implemented...
This paper analyzes the impact of Double Patterning Lithography (DPL) on 6T SRAM variability. A test chip is implemented in a 45nm CMOS process that uses DPL. Measurements from 75 dies demonstrate a significant impact of DPL on SRAM failures. Extensive analysis demonstrates that DPL induced mismatch considerably increases functional failures in SRAM cells, and degrades yield. We also propose a DPL-aware...
We propose a low power unified oxide and NBTI degradation sensor designed in 45nm process node. The cell power consumption is 105 lower than a previously proposed sensor. The unified nature enables efficient reliability monitoring with reduced sensor deployment effort and area overhead. Using the sensor Dynamic NBTI Management (DNM) has been implemented for the first time. DNM trades the excess `reliability-margin'...
A novel circuit switched swizzle network called XRAM is presented. XRAM uses an SRAM-based approach producing a compact footprint that scales well with network dimensions while supporting all permutations and multicasts. Capable of storing multiple shuffle configurations and aided by a novel sense-amp for robust bit-line evaluation, a 128×128 XRAM fabricated in 65nm achieves a bandwidth exceeding...
A new chip ID generation method is presented that leverages the random and permanent characteristics of oxide breakdown. A 128b ID array is implemented in 65nm CMOS and two algorithms for stressing the oxides are presented, showing a near-ideal Hamming distance of 63.92 in silicon measurements and consistent IDs across voltage and temperature.
This paper describes critical circuit building blocks for emerging sensing applications, particularly those where volume, and therefore power consumption constraints are orders of magnitude below current state of the art. Developments in ultra-low power microprocessors and memories are described, along with sub-nW timekeeping circuits, pW voltage references, and efficient DC-DC voltage conversion...
Chip lifetime degradation due to oxide breakdown is a major concern for today's designers. We review existing methods to solve the gate oxide reliability issues and also introduce an in situ degradation monitoring technique. This technique allows early detection of oxide degradation and makes a system aware of its reliability. When used in conjunction with reliability management schemes, it minimizes...
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