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A 128 kb portless SRAM is presented with 1024 rows per hierarchical bitline and CMOS thyristor-based local sense amplifiers. Each portless cell is 0.317 μm2 in 45 nm CMOS and consumes 50.8 fJ of energy per access at a 17.86 ns cycle time. A 65% read SNM improvement and a 33% leakage power reduction is achieved over a conventional 6T design. The thyristor-based sense amplifier occupies 2.4 μm2 and...
Driven by continued scaling of Moore's Law, the number of processing elements on a die are increasing dramatically. Recently there has been a surge of wide single instruction multiple data architectures designed to handle computationally intensive applications like 3D graphics, high definition video, image processing, and wireless communication. A limit of the SIMD width of these types of architectures...
Double patterning lithography (DPL) is widely considered the only lithography solution for 32nm and several subsequent technology nodes. DPL decomposes and prints the critical layout shapes in two exposures, leading to mismatch between adjacent devices due to systematic offsets between the two exposures. This results in adjacent devices with different mean critical dimension (CD), and uncorrelated...
Bell's Law predicts continual reductions in the size of computing systems. We investigate the status of the next paradigm shift that will usher in ubiquitous computing - sub-mm3 sensor nodes. However, this form factor remains beyond the capabilities of modern integrated circuit design techniques due to battery size. This paper describes new ultra-low power circuit techniques applied to digital processors,...
This paper analyzes the impact of Double Patterning Lithography (DPL) on 6T SRAM variability. A test chip is implemented in a 45nm CMOS process that uses DPL. Measurements from 75 dies demonstrate a significant impact of DPL on SRAM failures. Extensive analysis demonstrates that DPL induced mismatch considerably increases functional failures in SRAM cells, and degrades yield. We also propose a DPL-aware...
A novel circuit switched swizzle network called XRAM is presented. XRAM uses an SRAM-based approach producing a compact footprint that scales well with network dimensions while supporting all permutations and multicasts. Capable of storing multiple shuffle configurations and aided by a novel sense-amp for robust bit-line evaluation, a 128×128 XRAM fabricated in 65nm achieves a bandwidth exceeding...
An 8.75 mm3 sensor system is implemented with a near-threshold ARM Cortex-M3 core, custom 3.3 fW leakage-per-bit SRAM, two 1 mm2 solar cells, a thin-film Li-ion battery, and an integrated power management unit. The 2.1 ??W system enters a 100 pW data-retentive sleep state between sensor measurements and harvests energy from the solar cells to enable nearly perpetual operation.
Static noise margin analysis using butterfly curves has traditionally played a leading role in the sizing and optimization of SRAM cell structures. Heightened variability and reduced supply voltages have resulted in increased attention being paid to new methods for characterizing dynamic robustness. In this work, a technique based on vector field analysis is presented for quickly extracting both static...
Battery life is an important concern for modern embedded processors. Supply voltage scaling techniques can provide an order of magnitude reduction in energy. Current commercial memory technologies have been limited in the degree of supply voltage scaling that can be performed if they are to meet yield and reliability constraints. This has limited designers from exploring the near threshold operating...
SRAM dominates standby power consumption in many systems since the power supply cannot be gated as in logic blocks. The use of ROM for parts of instruction memory can alleviate this power bottleneck in mobile sensing applications such as implantable biomedical and environmental sensing systems, which can spend up to 99% of their lifetimes in standby mode. However, robust ROM design becomes challenging...
An integrated platform for sensor applications, called the Phoenix Processor, is implemented in a carefully-selected 0.18 mum process with an area of 915 times 915 mum2, making on-die battery integration feasible. Phoenix uses a comprehensive sleep strategy with a unique power gating approach, an event-driven CPU with compact ISA, data memory compression, a custom low leakage memory cell, and adaptive...
Subthreshold circuit design has become a popular approach for building energy efficient digital circuits. One drawback is performance degradation due to the exponentially reduced driving current. This had limited subthreshold circuits to relatively low performance applications such as sensor networks. To retain the excellent energy efficiency while reducing performance loss, we propose to apply subthreshold...
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