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This paper presents the new Write-Back scheme, which solve the half-select operation problem and faster than conventional Write-Back technique for memory array with seven-transistor (7T) single-ended static random access memory (SE-SRAM) bit cell. Data in the cells are sensitive and flipping can happen, so proposed scheme improves the stability issue for half-selected cells without performance degradation.
This paper presents a method of power optimization, implemented on Open RISC processor, aimed at reducing dynamic and static power consumption. Multi-voltage design method is one of the effective power reduction methods, implemented by dividing circuit into separate power domains based on their power/performance requirements. Multi-voltage will combination with multi-threshold and power gating techniques...
In modern System on Chips (SoCs) different blocks may use clock signals with different frequencies, in which case SoC is said to have multiple clock domains. The signal that travels from one clock domain to another needs to be synchronized in the receiving domain to prevent occurrence of metastability phenomenon, i.e. a degradation of a signal. Synchronization is implemented by so called synchronizing...
This work presents the design and implementation of a power-efficient 2-tap feed-forward voltage mode driver which has impedance tuning and signal conditioning capabilities. The driver has a robust mechanism to match its impedance to the line impedance even when signal conditioning is enabled which minimizes reflection and improves signal quality. A mixed signal approach that detects and compensates...
In this paper a new approach for on chip compensation of resistor value which can change due to process and temperature variations is presented. There is a special circuit which generates three bits for compensation corresponding to the variation of termination resistor value. The generated bits connect compensation resistors to termination resistor in parallel and in series through demultiplexor...
A novel approach for process variation detection (PVD) is proposed. Named "dynamic measurement", the proposed method is able to detect process corner type. Information on process variability is represented in digital signal (code). Use of such approach can exclude necessity of use of special measurement equipment or embedded test structures (ring oscillators, transistor arrays, etc.) during...
A low power method of clock signal duty cycle adjustment is presented in this paper. The proposed architecture produces a synchronous signal in the output of system with 50±1% duty cycle over PVT, which is needed to avoid data error and setup/hold time margins violations during farther operation with data. Method also helps to improve noise immunity, because in case of 50% duty cycle signal in the...
This paper presents method of power optimization implemented on RISC architecture ORCA processor with the help of clock gating and multi-threshold approach aimed at significant reduction of dynamic (switching) power and leakage power. The results are compared with previous research implementing other low power technique on the same processor and with standard design.
The paper presents a multi-topology step-down switched-capacitor (SC) converter with a novel adaptive control. The control system adjusts the number of SC cores to significantly reduce output voltage ripple, as well as performs dynamic frequency control depending on actual load of the converter. By means of new dynamic control system, the converter achieves 50ns response time and 24mV of maximal output...
Recognition task is a hard problem due to the high dimension of input image data. The principal component analysis (PCA) is the one of the most popular algorithms for reducing the dimensionality. The main constraint of PCA is the execution time in terms of updating when new data is included; therefore, parallel computation is needed. Opening the GPU architectures to general purpose computation allows...
A method of resistance calibration without external precision elements usage presented in paper. In the proposed method, used structures which operation based on technologically accurate elements and signals to have high accuracy resistance after calibration. Architecture produces a calibration code corresponding to 50Ohms PVT compensated termination impedance, which is needed to avoid reflections...
A design and simulations methodology that detects and compensates for NMOS and PMOS transistor resistance variation is presented. The proposed methodology provides a robust mechanism to match the transmitter impedance to the line impedance which minimizes reflection and improves signal quality. A mixed signal approach, where an analog circuit detects the resistance variation, and a digital circuit...
Due to the rapid development times, device complexity, etc. of the semiconductor industry it is challenging for universities to teach modern Integrated Circuit (IC) design. In particular, universities lack access to the necessary semiconductor technology data required to implement educational projects, as this information is normally proprietary. Additionally, access to state-of-the-art designs is...
Methods of CMOS resistance process voltage temperature variation detection and compensation are described. Two different approaches are proposed and comparative analysis is performed. The first solution makes use of an external precise resistor as a variation reference, while the second one uses reference clock frequency for the same purpose. Detection of variations is realized using the proposed...
An on-die capacitor mismatch elimination method, using reference clock and dc current is presented. The proposed method provides opportunity to measure the difference of the two uniform capacitor values, detect the mismatch due to technology process deviations, and bring it to minimum. In this paper a self-calibration (self-regulation) technique for two identical capacitor mismatch elimination is...
This paper addresses a new approach for low jitter, low power phase locked loop design. Effects of process-voltage-temperature variation on PLL are studied. A self compensating PLL solution using process-voltage-temperature variation effects compensation method, based on external reference clock signal is presented. The proposed solution shows considerable improvement of frequency stability and power...
The paper presents an investigations of various noise effects on frequency stability of differential ring voltage controlled oscillators. The impact of bias generator parameters and PVT variations on noise immunity is demonstrated and simplified models are developed. A method of bias generator parameter calculation and PVT compensation is suggested. The efficiency of the developed means is tested...
A method of NMOS and PMOS transistor resistance variation detection and compensation, using reference clock frequency is presented. The proposed method provides opportunity to measure and compensate MOS device resistance deviation, due to technology process, voltage and temperature variations, separately. Detection of variations is realized using the proposed digital logic block. Efficiency of the...
A method of receiver and transmitter input/output resistance calibration, using external reference resistor is presented in this paper. The proposed architecture produces a calibration code corresponding to 50-Ohm PVT compensated termination impedance, which is needed to avoid reflections in transmission lines. The presented calibration mechanism can be used in the special input/output circuits of...
Unified Power Format (UPF) is an industry wide power format specification to implement low power techniques in a design flow. UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts help describe power intent such as: which power rails to be routed to individual blocks, when blocks are expected to be powered up or shut down, how voltage levels should be shifted...
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