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We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs...
We demonstrate, for the first time, scaled hybrid inverters built in a 3D Monolithic (3DM) CMOS process featuring short-channel replacement metal gate (RMG) InGaAs-OI wide-fin/planar nFET top layer and SiGe-OI fin pFET bottom layer. We achieve state-of-the-art device integration, using raised source drain (RSD) on both levels and silicide on bottom pFETs. Bottom SiGe-OI pFETs are scaled down to sub-20...
We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and...
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