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This paper addresses the problem of optimal hardware-realization of finite-word-length (FWL) linear controllers dedicated to MEMS applications. The biggest challenge is to ensure satisfactory control performances with a minimal hardware. To come up, two distinct but complementary optimizations can be undertaken: in control theory and in binary arithmetic. Only the latter is involved in this work....
ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. Weshow how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we...
Optimizing the number of additions in constant coefficient multiplication is conjectured to be a NP-hard problem. In this paper, we report a new heuristic requiring an average of 29.10% and 10.61 % less additions than the standard canonical signed digit representation (CSD) and the double base number system (DBNS), respectively, for 64-bit coefficients. The maximum number of additions per coefficient...
In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general space-time partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (N/r), but also eliminates the need of pre-computing odd multiples of the multiplicand in higher radix (r≥3) multiplication. Based on a mathematical proof that...
This paper summarizes the necessary steps we went through to develop a design-kit for full-custom design based upon ISiT's CMOS 1 μm technology process. All basic information dealing with technology setup, rule decks and analog simulation environment is provided and commented. The design-kit is fully compliant with Cadence Generic Process Design-Kit (GPDK) methodology guide, revision 1.8, September...
SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers. In conformity with design-reuse methodology, this paper introduces high-quality SPI Master/Slave IPs that incorporate all necessary features required by modern ASIC/SoC applications. Based upon Motorola's SPI-bus specifications, version V03.06, release February 2003, the...
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