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In this paper, we propose and compare two architectures of HW/SW interface logic in FC-2, namely as TX/RX scheduler and TX/RX controller. The comparison result shows that the TX/RX controller is more efficient than the TX/RX scheduler. The TX/RX controller is implemented in the proto Fiber Channel (FC) chip fabricated in a 0.18um CMOS technology with six layers of metal. The gate count of TX/RX controller...
The area, speed, and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digital filter, so the performance of digital system is determined by multiplication. This paper compares four different popular methods: Conventional multiplications and additions; full custom...
The mixed optimization method proposed in this paper combines analysis of multi-level protocols with extraction of single-level protocol flow chart to design the accelerating hardware to improve the performance of FC-2. We implement the accelerating hardware with 0.18 CMOS standard technology. Compared with the frame based design method, the proposed method can improve the performance by 4.5 times...
This paper describes a low-noise low-offset CMOS readout circuit for MEMS capacitive accelerometers. It employs a feedback capacitance and a combination of switches to have the input parasitic capacitance and the offset voltage canceled. The raised current IDS of the input differential pair in the first stage is used to help reduce sharply the total low-frequency noises without increasing the complexity...
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