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This paper proposes a full-featured Verification Intellectual Property (VIP) which can be used in functional verification at transaction level. The VIP includes a gold testcase set, a hierarchical testbench and a functional model. Firstly, the natural language specification is quantified and converted to the structured specification models. Secondly, the models are transformed into the codes of testcase...
To simplify the design & verification complexity and speed up design, a data flow driven hardware description method and its circuit synthesis based on operators are proposed. The behavior of each data is described precisely using a high level abstract language which is quite similar to ANSI C. The compilation tool ReCom compiles data flow driven description into circuit based on operators. There...
The encoder and decoder are the keys of security and error-rate for UHF RFID reader. In this paper, we present a multi-bit encoder and FM0/Miller decoder design which has less error-rate and more security. We take resource reused, no-gap-link between different data areas of encoder, and low power into consideration in our design. FM0/Miller decoder can handle a ± 25% data rate variation and the error-rate...
With the complexity of IC design increasing, it becomes an emergent issue to reduce the cost and short time-t o-market of design. In this paper, we propose a high-level synthesis method for Reconfigurable Operator Array. The high-level synthesis compiler ReCom is proposed to synthesize the high-level abstract description to low-level hardware description. Meantime, three languages are proposed to...
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