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Due to the difficulty of tracking large numbers of new migrants, how their daily activity behaviors differ from those of settled residents has not been well investigated, leading to a lack of understanding of new migrants' integration. Meanwhile, existing research largely emphasized residential space and ignored other activity disparities. To obtain a more comprehensive picture of urban segregation,...
A digital calibration method is presented for delta-sigma ADCs with focus on feedback DAC mismatch error correction. The DAC mismatch information is acquired, and then the nonlinearity is cancelled in the digital domain while the ADC operates. Unlike dynamic element matching which is commonly run between non-overlapping clock phases, the proposed method does not have the restriction and introduces...
A third-order switched-capacitor low-distortion delta-sigma ADC with shifted loop delays (SLD) is described, and its performance is discussed. It can relax the speed requirements of the quantizer and the dynamic element matching (DEM) block, and eliminate the last stage adder. An implemented 0.18 um CMOS prototype with the proposed architecture provided 81.6 dB SNDR, 81.8 dB dynamic range, and −95...
A multi-channel mixed-signal noise source with uniform amplitude distribution is presented. Cross-coupled, counter-propagating linear feedback shift registers are used to produce mutually independent binary distributed noises, which in turn generates mutually independent uniformly-distributed discrete-analog noises after digital-to-analog conversion. A stochastic comparator offset cancellation technique...
A radix-based digital technique for compensating capacitor mismatch in a two-capacitor DAC is described. Digital input words are pre-distorted with a serial ADC-like algorithm before they are fed into the DAC. The proposed methods provide excellent linearity performance when the DAC is converting a high number of bits. Extra peripheral circuits to achieve the digital compensation are briefly discussed.
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