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We utilize eye-diagram measurements of timing jitter to investigate the impact of PBTI in devices subject to DC as well as ring oscillator (RO) and pseudo-random binary sequence (PRBS) stress waveforms. We observe that RO measurements miss the relevant random timing jitter increases which are well captured using PRBS measurements. We also observe that DC, RO, and PRBS stresses all introduce similar...
The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored...
SILC analysis is a powerful tool for the assessment of breakdown characteristics of high-kappa devices. By applying the SILC analysis during high field stress, we determined that the degradation mechanism for LaOx capped devices was drastically different as compared to the conventional Hf-based gate stacks. The La atoms diffused into the interfacial layer disrupting the SiO2 structure which may affect...
La-doped HfSiO samples show lower threshold voltage (Vth) and gate current (Igate), which is attributed to dipole formation at the high-k/SiO2 interface. At low and intermediate field stress, La-doped devices exhibit better immunity to positive bias temperature instability (PBTI) due to their lower charge trapping efficiency than the control HfSiO, which mainly results from a dipole-induced greater...
New hot-carrier degradation phenomenon that depends on gate bias in nano-scale floating body MOSFETs is identified using 2-D device simulation and hot-carrier injection measurements. In the case of sufficiently high gate voltage, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension resulting in impact ionization at the source as well as drain junctions...
Sample devices were fabricated with 2.0 nm SiO2 and 2.5-10.0 nm HfO2. Transistor transconductance and gate leakage were used to evaluate PID. BTI and dielectric breakdown were measured to study the PID effect. For both nMOSFETs and pMOSFETs, the transconductance was degraded for the different antenna structures. It was found that, even below 0.9 nm of EOT range, the plasma charging damage was observed...
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