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Boundary and edge cues are highly beneficial in improving a wide variety of vision tasks such as semantic segmentation, object recognition, stereo, and object proposal generation. Recently, the problem of edge detection has been revisited and significant progress has been made with deep learning. While classical edge detection is a challenging binary problem in itself, the category-aware semantic...
Over the years, computer vision researchers have spent an immense amount of effort on designing image features for the visual object recognition task. We propose to incorporate this valuable experience to guide the task of training deep neural networks. Our idea is to pretrain the network through the task of replicating the process of hand-designed feature extraction. By learning to replicate the...
In many implementations of intelligent traffic system (ITS), the actuated signal controller (ASC) is widely deployed to control the traffic lights and other terminals. However, inadequate research has been done on the security for the link that goes between the ASC (e.g., primary device) and many secondary devices controlled by the ASC. The communication of the link is based on the old synchronous...
We have designed pass-transistor logic (PTL)-based D flip-flop and T flip-flop to be used in finite field multiplication. Since both CMOS and PTL have their respective advantages in area, speed, and power, we have compared two different designs (conventional implementation and improved implementation) of serial-parallel finite field multiplication using pure CMOS, pure PTL, and hybrid PTL/CMOS logic...
Two processor designs are presented that can compute CORDIC rotation and vectoring operations in floating-point representation. In order to achieve the required accuracy, we partition the computation into two phases: coarse and fine, and look for efficient design approaches to minimize the area cost as well as the latency. The proposed architectures can perform floating-point CORDIC in both vectoring...
A low hardware cost low-density parity-check (LDPC) decoder is presented in this paper. Using logical OR operation in the check nodes for the log sum-product algorithm (Log-SPA), we propose a new architecture for updating the check nodes messages. Synthesized and numerical results show that the proposed architecture achieves up to 21% total hardware reduction with fair BER performance when compared...
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