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A flash memory cell with 90nm ground-rules has been embedded in a high performance (HP) CMOS logic process. A novel deep trench isolation (DTi) process module enables an isolated pwell (IPW) bias scheme, leading to flash with uniform channel program/erase (UCPE) by Fowler-Nordheim (FN) tunneling without GIDL, a key feature for low-power (LP) electronics. IPW leads to a compact cell design and a highly...
In this work, we present a novel buried BL (BBL) concept that links the source contacts of each individual BL via the isolated p-well; thus effectively eliminating one metal line per BL and reducing overall cell size. In comparison to the UCPE cell, a conservative cell size shrink of about 40% can be achieved from a standard embedded 21F2 DT-UCPE-cell. The schematic cell layout is shown and comparison...
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