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Processor hardware has been architected with the assumption that most data access patterns would be linearly spatial in nature. But, most applications involve algorithms that are designed with optimal efficiency in mind, which results in non-spatial, multi-dimensional data access. Moreover, this data view or access pattern changes dynamically in different program phases. This results in a mismatch...
A polymorphic system consists of heterogeneous cores such as CPU, GPU, FPGA, and ASIC cores. A polymorphic thread is compiled for multiple morphisms afforded by these diverse cores. The resulting polymorphic computing system can solve two problems - (1) Polymorphic threads enable more complex, dynamic trade-offs between delay and power consumption. A piecewise cobbling of multiple morphism energy-delay...
Integration of multiple processing cores and variegated custom hardware functional units in recent embedded system chips favor network-on-chip (NOC) communication architecture for optimal utilization of these components by applications. Application design paradigms for such embedded systems should aim to improve the overall user experience of the system instead of optimizing traditional design parameters...
Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set...
The complexity of current day embedded systems is steadily on the rise due to innovative content consumption applications. Embedded systems have to be adaptable and scalable to meet the unique resource demands of such applications to deliver satisfactory performance. Effective sharing of system resources by content consumption applications is imperative for user satisfaction. In this paper, we address...
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