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Using an advanced thin wafer technology, we have successfully fabricated the next generation 650V class IGBT with an improved SOA and maintaining the narrow distribution of the electrical characteristics for industrial applications. The applied techniques were the finer pattern transistor cell, the thin wafer process and the optimized back side doping concentration profiles. With the well organized...
In this paper, we investigate a mechanism of drain-voltage oscillation of MOSFET under high dV/dt UIS condition by using numerical simulation and experiments. One of the trigger events of the oscillation is found to be the current path switching between the active region and the termination region with close BVDSS characteristics. By optimizing the device parameters to make appropriate the BVDSS balance,...
This paper presents high temperature performance of CSTBT™ (III) and its main parameters. The key for high temperature operation is suppressing the parasitic NPN transistor action. N+ emitter width, P+ diffusion layer depth and gate oxide thickness are main parameters for suppressing the parasitic action. The optimized 1200V CSTBT™(III) succeeded in 200°C operation without any thermal runaway or turn-off...
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