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In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive...
Commonly, two main classes of formal testing techniques are applied to check the conformance of protocols and software: active and passive testing (monitoring) techniques. Because of many industrial constraints such as the necessity to achieve implementation black box testing, passive testing techniques become highly relevant in several cases. Besides, most of the passive testing techniques only consider...
This paper deals with a new and low cost embedded DRAM (eDRAM) architecture. COLK (Capacitor Over Low K) cell with capacitor placed in the first and thick SiO2 dielectric has been successfully integrated. 4Mb eDRAM testchip using this new architecture is functional in 45 nm node and presents good yield. Moreover we succeed to demonstrate the capability to continue downscaling of eDRAM for nodes down...
Although the adoption of the IP Multimedia Subsystem (IMS) keeps growing, IMS applications are often integrated to the system without being formally tested. In this work, we are interested in the IMS Push over Cellular (PoC) service, an OMA standard. We propose a conformance passive testing approach to check that its implementation respects the main standard requirements. This approach is based on...
A new triple-gate transistor, formed by recessing the oxide layer in the isolation trenches, without any other significant modification in the conventional planar transistor process flow, is evaluated as the access transistor of the 65 nm node embedded DRAM (eDRAM) memory cell. In addition to the own advantages of this structure (high on-state current (Ion), small Body Bias Effect (BBE), excellent...
For the first time, we report a complete evaluation of a TiN/ZrO 2/TiN stacked capacitor suitable for 45 nm embedded DRAM (eDRAM). Indeed, this study, done on a real integration (65 nm 3D stacked capacitor flow), shows that zirconium oxide, deposited at low temperature (275degC) by atomic layer deposition (ALD), meets all the 45 nm eDRAM specifications: an equivalent oxide thickness (EOT) below 8...
Plasma lipoproteins are continuously remodeled through the actions of enzymes and of specialized lipid transfer proteins. The transfers of cholesterol esters and triglycerides are mediated by the cholesterol ester transfer protein (CETP), while that of phospholipids is facilitated by both CETP and the phospholipid transfer protein (PLTP). In contrast to CETP, PLTP has been reported to be a thermolabile...
We report the fabrication of etched-groove silicon permeable base transistors (PBTs) with mushroom-shaped 0.2-0.4 ??m wide source fingers. This structure enables both the passivation of the Si finger sidewalls and the reinforcement of the platinum gate with a gold overlayer. The low base resistance and the optimized doping profile yielded devices with fT and fmax values up to 26 GHz.
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