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The system-level reliability of solid-state drives (SSDs) is investigated with 1X, 2X and 3Xnm NAND flash memories. The reliability degradation of NAND with scaling is an serious issue. Advanced ECC with signal processing such as error-prediction low-density parity-check (EP-LDPC) and error recovery (ER) scheme will be needed in the future SSDs. In this paper, the NAND reliability information used...
This paper presents intelligent solid-state drives (SSDs), which decrease memory errors by 95% and reduce power consumption by 43%. Figure 11.4.1 shows the measured memory cell error in the data retention and program disturb of 4X, 3X and 2Xnm NAND flash memories. As the memory size decreases, both data retention and program disturb errors increase due to the interference, random telegraph noise and...
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. Two types of electron injection scheme: both side injection scheme and self-repair one side injection scheme are analyzed comprehensively for 65nm technology node 8T-SRAM cell and also for 6T-SRAM cell. This paper shows that in the 6T-SRAM with the local injected electrons the read...
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is proposed for the first time. The asymmetric VTH shift is doubled from the conventional scheme without process and area penalty. Measurement results show 24% increase in SNM without write degradation by the asymmetric PG transistor. 70% read margin enhancement is achieved by the proposed...
A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By monitoring the error number or the write / erase cycles, the ECC codeword dynamically increases from 512Byte (+parity) to 1KByte, 2KByte, 4KByte...32KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. As a result, the acceptable raw bit error rate, BER, before ECC...
A 0.5V 6T-SRAM with ferroelectric (Fe-) FETs is proposed and experimentally demonstrated for the first time. The proposed SRAM has a unique configuration to apply the body of NMOS and PMOS with VDD and VSS. During the read and the hold, the VTH of Fe-FETs automatically changes to increase the static noise margin, SNM, by 60%. During the sand-by, the VTH of the proposed SRAM cell increases to decrease...
A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.
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