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The paper presents a method for automatic RTL-interface synthesis for a given C++ function as well as for a given SystemC-interface. This task is very important in High-Level Synthesis design flow where design entry is usually done in some abstract language (e.g. C++). As a source high-level description targets different SoC architectures or protocols, so it is needed to generate relevant pin-level...
We consider a high performance software/hardware implementation of fault and fault -free simulation methods, and linting-technology for early design stage verification as well. Application of these technologies allows significant increasing simulation performance in comparison with software tools, and reducing design time of very high scale integrated circuits for 20-30%.
Existing software in Electronic Design Automation shows lack of dual-core processors support. As a result, we see bad processing resources utilization. This work is devoted to exploration of existing approaches to parallel logic and fault simulation on dual-core workstations.
This paper offers approach to complex digital system testing based on hierarchy scaling during diagnosis experiment. Several models of testing are proposed. Main principles of testing system organization are given. Such approach allows significant reducing overall system testing and diagnostics time.
A new technique of assertion mechanism for digital SoC diagnosis and functional verification is proposed. The developed mechanism can be effectively applied on the early stages of design as well as on the implementation phase. The IEEE 1500 SECT standard technologies are used for signals observation
A high performance fault simulation method based on the superposition procedure is offered. It is oriented on large digital designs processing. Evaluation of RT and gate level design description is proposed in this work. The data structure and program are developed for algorithms' realization of the proposed method and integration with automatic test pattern generation systems.
Fast backtraced deductive-parallel fault simulation method oriented on processing of complex digital devices containing hundreds of thousand equivalent gates is offered. Data structures and algorithms for method realization are described
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