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This paper reviews the progress in testing standards, characterization methods as well as protection techniques against the Charge Device Model (CDM) ESD event. The paper also discusses recent development trends in this field.
A new methodology for evaluating the effectiveness of CDM protection is presented. VFTLP measurements are performed on structures composed of an ESD protection device in parallel with a gate monitor device; a MOS transistor or inverter. Parametric shifts in threshold voltage, VTH, as well as drain saturation current, IDD, of the MOS monitor device are measured to continuously gauge the extent of the...
Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.
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