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In this paper, we propose a dynamic voltage scaling (DVS) policy for a fully asynchronous NoC suitable for low-power yet high-performance architectures. The DVS policy is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision. It judiciously adjusts switch voltage among only three voltage modes. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations...
Increasing diversity in packet-processing applications and rapid increases in channel bandwidth lead to greater complexity in communication protocols. These factors result in larger computational loads for packet-processing engines that introduce high performance microprocessor designs as an important solution. This paper presents an exhaustive simulation for exploring the performance of instruction-level...
Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling energy dissipation of embedded systems. However, recent researches have illustrated that DVFS techniques have compromising effects on the system reliability. Our analysis results show that, ignoring the effects of voltage scaling on fault rate could considerably decrease the system reliability. Therefore, we use the...
In this paper we evaluate the compromising effect of energy saving and throughput degradation on a fully asynchronous NoC architecture with regards to the dynamic voltage scaling guidelines. The investigated fully asynchronous NoC architecture is suitable for GALS-based MPSoCs architectures. The introduced architecture is simulated in 90nm CMOS technology with accurate Spice simulations, where the...
Dynamic voltage and frequency scaling (DVFS) is an effective method for controlling both energy and performance of a system. Since the increasing rate of radiation-induced transient faults depends on operating frequency and supply voltage, DVFM techniques are recently shown to have compromising advantages on electronic system reliability. Therefore, ignoring the effects of voltage scaling on fault...
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