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An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm2 of chip area.
High speed DACs and ADCs are key components for mm-wave communication systems that apply spectral efficient modulation formats to achieve date rates up to 100 Gbit/s. CMOS converters enable the integration with a mm-wave front-end and a high-throughput DSP on a low-cost system-on-chip. We present CMOS ADC and DAC prototypes with conversion rates up to 36 GS/s, resolutions between 3 and 6 bit and real-time...
This paper presents a 6-GS/s 6-bit time-interleaved successive approximation register (SAR) analog to digital converter (ADC) realized in 90-nm CMOS. The ADC consists of 32 single SAR-ADCs. The measured effective-number-of-bits (ENOB) at sampling rate of 6.144 GS/s are 5-bit at DC and 3.6-bit at the Nyquist frequency. The power consumption of the ADC-core without I/O's and 4-to-1 output MUX is 359...
A transimpedance amplifier (TIA) in 1-µm InP technology for the application in next generation fiber optical data communication systems is presented. The TIA exhibits a bandwidth of 45 GHz, a differential transimpedance of 70dBOhm and a total harmonic distortion (THD) below −30 dB up to a differential output voltage of 500mV-PP.
A novel architecture of a track and hold (T&H) circuit for the realization of a high speed analog demultiplexer is presented in InP DHBT Technology. The architecture allows a sampling rate flexible demultiplexing of an analog input signal. The demultiplexer features a measured THD above 32 dB and a SFDR above 35 dB with a differential input voltage of 0.5V-PP when operating at 25 GHz. This allows...
A 36GS/s 3bit flash ADC with a large analog input bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is about 2 bit up to 20GHz input signal frequency at a sampling rate of 36GS/s. The power consumption of the ADC core is 2.6W, the core area is 0.16...
An analog 2:1 multiplexer for high speed analog multiplexing is presented in InP DHBT technology. The multiplexer features a SNDR above 26 dB with a differential input voltage of 1V-PP and a 3 dB corner frequency above 40GHz. The power consumption of the multiplexer is 1.35W at a supply voltage of 5.5V. The multiplexer is suitable for the realization of a 50GS/s digital-to-analog conversion system,...
A 25 GS/s 6 bit flash interpolating ADC in 90 nm CMOS technology with an analog input bandwidth of 14 GHz is presented. The ADC is realized in a fourfold parallelized structure to increase the sampling rate and to increase the available settling time in the single ADCs. To improve the linearity several calibration methods are implemented in the circuit. The power consumption of the whole ADC is 2...
A linear buffer for high speed demultiplexing is presented in InP DHBT Technology. The buffer has a SNDR of 38 dB with a differential input voltage of 500mV-PP and a 3 dB corner frequency above 50 GHz. The power consumption of the buffer is 0.5W at a supply voltage of 5V. The buffer is suitable for applications which need a low amplification and a high output bandwidth e.g. in a high speed demultiplexer...
A pseudo segmented twofold time-interleaved 6-bit digital-to-analog converter (DAC) occupies 0.28 mm2 chip area in a standard 90 nm CMOS technology. The DAC enables sampling rates up to 28 GS/s with a power consumption of 2.25 W at a −2.5 V power supply. The output bandwidth is at least 14 GHz. The integral non-linearity (INL) and the differential non-linearity (DNL) are 0.8 LSB and 1 LSB respectively...
A 20 GS/s 3 bit flash ADC with a wide analog bandwidth is realized in a 65 nm CMOS technology. By employing a fourfold parallelization a high sampling rate is achieved, while a large input bandwidth is maintained. The measured effective resolution is between 2 bit and 2.5 bit at a sampling rate of 12.8 GS/s and between 2 bit and 2.3 bit at a sampling rate of 18 GS/s. The power consumption of the ADC...
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