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In the development of high density DRAMs such as 1 M bit or beyond, it will be increasingly important to achieve high speed, competitive to SRAMs, in addition to low cost per bit. Recently, BIPOLAR CMOS (BICMOS) technology has been proposed for achieving high speed and low power operation, especially SRAMs (1,2).
The compact and low power logic circuit design for multi-pillar vertical MOSFETs has been proposed. The proposed design with the multi-pillar vertical MOSFETs is very practical for considering the load capacitance and resistance by changing the number of the silicon pillars flexibly for the desired channel width of series connected MOSFETs and their layout pattern.
By utilizing the vertical MOSFETs advantages, the compact, efficient, and low-power peripheral core circuit design for the NAND Flash memory has been proposed.
The DC and AC characteristics of the multi-pillar vertical MOSFET's have been studied, considering the silicon pillar diameter thinning cases due to the process fluctuation. In order to suppress the pillar thinning influences, the Inter Contacts design has been proposed, which can realize the compact, high-speed, low-power, and stable circuits with the multi-pillar vertical MOSFET's.
This paper is devoted to examining the impact on the charge pump performance by utilizing the merit of the back-bias effect free for the vertical MOSFETs. The simulation results indicate that the Charge Pump circuits composed of the Vertical MOSFETs (Vertical CP) can drastically shrink the charge pump area and lower the power consumption in comparison with the Charge Pump composed of the Planar MOSFETs...
This paper is devoted to examining the asymmetric characteristics of the conventional vertical MOSFET, proposing a new vertical MOSFET which can suppress the asymmetric characteristics, and validating its impact on an ultra compact and robust logic circuit.
Improvements in data retention characteristics of a FETMOS cell which has a self-aligned double poly-Si stacked structure are discussed. The improvement results from the use of a uniform write and erase technology. Experiments show that a gradual detrapping of electrons from the gate oxide to the substrate effectively suppresses data loss of the erased cell which stores positive charges in the floating...
This paper describes the dramatic improvement in data retention characteristics by using a uniform write and uniform erase technology, performed by uniform injection and uniform emission over the whole channel area of the FETMOS cell, which has a self-aligned double poly-Si stacked structure. It is clarified experimentally that gradually detrapping electrons from the gate oxide to the substrate effectively...
A novel SRAM (static random access memory) cell, which consists of a bipolar transistor and an MOS transistor, is proposed. The device, which is based on the reverse base current (RBC) effect, has been fabricated by conventional BiCMOS technology, using double poly-Si. A cell size of 8.58 mu m/sup 2/ has been realized in a 1.0- mu m ground rule. The results indicate that the RBC cell can be applied...
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