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Design of power delivery networks for printed circuit boards hosting both analog and digital parts often employs small power islands for supplying power to sensitive components. While providing necessary isolation from noise generated by other components, the power islands also experience increased inductance due to current crowding at the bridge. In this paper, the inductance at a port on the power...
This paper presents a mechanism to remove artificial plane resonances using matched termination when analyzing signal channels in a multilayered PCB using a mix of 3D and hybrid boundary element based methodology to model the via transitions and routing areas, respectively.
Power delivery network (PDN) design is becoming even more critical with the advent of progressively complex environments on and beyond the die. Multicore chips, mixed-signal designs with multiple reference voltages, and complex 3D packaging situations lead to complicated PDN geometries with high-frequency demands and sharpening edge rates even when on-core frequencies are relatively constant. Early...
In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented...
This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-duration profiles, and can be used to derive a noise susceptibility metric for the noise robustness of logic gates. Analytical methods - based upon calibration runs in circuit simulators - to determine noise susceptibility in...
Future integrated circuits are characterized by their high defect rates thereby necessitating certain degree of redundancy. In a typical network-on-chip (NoC), multiple paths exist between a source and a sink to provide the required level of fault tolerance. Consequently, a manufacturing fault on a single interconnect does not necessarily render the resulting integrated circuit useless. In this paper...
An analytical model for the upper bound of loop self inductance has been developed that is applicable to a wide range of layout geometries commonly encountered in high performance integrated circuits. We demonstrate that the existing analytical models can significantly underestimate the value of loop self inductance producing optimistic results. When compared with field solver results, the developed...
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