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In this paper, a low-power motion estimation designed chip was proposed for wireless panoramic endoscope system. This design consists of the motion estimation system and implemented by a low-power hardware design technique. There are two parts to the architecture of the motion estimation system. The first part is the one-dimensional processing element array to calculate the absolute difference. The...
Data hazards cause severe pipeline performance degradation for data-intensive computing processes. To improve the performance under a pessimistic assumption on the pipeline efficiency, a high-speed and energy-efficient VLSBM is proposed that successively performs a speculating and correcting phase. To reduce the critical path, the VLSBM partial products are partitioned into the -bit least significant...
The purpose of this study was to understand how to use Augmented Virtuality (AV) to improve the training of intercollegiate archers and to understand the correlations among their levels of physical activity, health-related quality of life and archery performance in AV and 70M outdoor target archery competitions. The study employed cross-sectional study design and recruited 31 intercollegiate archers...
In a digital circuit system, IR drop effect can be alleviated by reducing the peak current of the system. Clock skew scheduling is a popular technique for peak current reduction. In this paper, we propose two algorithms that apply a Multiple Threshold CMOS (MTCMOS) technique rather than clock skew scheduling to do peak current reduction. MTCMOS techniques are feasible to reduce peak current because...
In a typical synchronous SoC design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose...
A conventional 2-dimensional (2D) systolic processing element (PE) array of a chip used for implementing full aearch block matching algorithm (FSBMA) needs a large number of input pads to read sequence image data from SRAM chips. In our work, we embed SRAMs in the FSBMA chip and the PEs read the sequence image data from the embedded SRAMs quickly and directly. Three embedded SRAM arrays are used to...
In a typical synchronous circuit system, a large peak current occurs near the time of an active clock edge because of the aggregate switching of a large number of transistors. A huge peak current causes circuit designers to increase the power pad number for preventing voltage drop problem. The number of aggregate switching gates can be cut in half at most if the circuit system can use a clock scheme...
In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional CMOS gates. Compared with the...
Clock skew scheduling for peak current reduction is a conventional technique for solving IR-drop problem in physical design stage. In this paper, we propose two kinds of long delay flip-flops and a heuristic algorithm that is used to resynthesized flip-flops of a circuit. Because the switching times of flip-flops in the resynthesized circuit are staggered, the IR drop effect can be reduced. Unlike...
Because the leakage current of a digital circuit depends on the states of its logic gates, assigning a minimum leakage vector (MLV) to the primary inputs and the flip-flops' output pins of the circuit that operates in the sleep mode is a feasible technique for leakage current reduction. In this paper, we propose a novel probability-based algorithm and technique that can rapidly find an MLV. Unlike...
Traditionally, it is assumed that every variable in the input HDL (Hardware Description Language) behavioral description needs to be held in a register; A register can be shared by multiple variables if they have mutually disjoint lifetime intervals. This approach is effective for signal-flow-like computations such as various DSP algorithms. However, it is not the best for the synthesis of control-dominated...
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