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In this paper, a time-mode resonator is presented that is used to realize a second-order bandpass ΔΣ time-to-digital converter (TDC). The resonator is constructed as a cascade of two lossless discrete-time integrators implemented using time-latches and some digital logic in a negative feedback configuration. This paper presents for the very first time the means in which time-mode circuits are used...
In this article, a method of designing high-order DLLs is presented and verified through both simulations and physical experiments. The general approach is based on selecting the transfer function of the closed-loop DLL and deriving the loop filter behavior based on the gain of the phase-detector and voltage-controlled delay line. The proposed approach does not rely on the principle of design based...
This paper presents a CMOS track and hold amplifier (THA) designed and fabricated in a 130 nm CMOS technology. It is intended for analog-to-digital converters (ADCs) used in radio receivers that sample in the Giga-Hertz region. At these data rates, it is extremely difficult for data converters to reach the desired performance levels using a single data path. Rather, ADCs operating in parallel at lower...
In this paper we present an implementation and performance investigation of a phase signal generator for use in mixed-signal embedded test. The generator consists of a circular 1×N-bit memory and a time-mode filter. The memory is loaded with a phase-modulated sigma-delta encoded bit stream generated in software. Due to its digital nature, the generator except for the time-mode filter is fully synthesizable...
This article presents techniques and circuits for jitter generation and measurement. The proposed implementations use periodic bit-streams and high-order PLLs to generate the desired phase signal. Here, an arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the phase-domain through a digital-to-time converter (DTC) process realized in software...
In this paper we present a technique that permits the correction of errors caused by the timing jitter associated with sampling clocks cadencing analog-to-digital converters (ADCs). The correction system is digital, completely independent of the front-end ADC and corrects the data out of the converter on a sample-to-sample basis. Relative to the ADC under consideration, the proposed technique enables...
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