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To improve power system reliability, a protection mechanism is highly needed. Early detection can be used to prevent failures in the power transmission line (TL). A classification system method is widely used to protect against false detection as well as assist the decision analysis. Each TL signal has a continuous pattern in which it can be detected and classified by the conventional methods, i.e...
This paper proposes hardware architecture of WiMAX OFDMA frequency domain processing system. The system mainly consists of channel estimator, equalizer, and subcarrier de-allocator. The system is optimized for flexible and re-configurable WiMAX OFDMA receiver. The flexibility feature is obtained by employing flexible control unit approach using task FIFO. Using this scheme, the designed system can...
This paper presents a new, unique two-dimensional 8 × 8-point DCT architecture design which employs direct 2-D DCT approach with regular butterfly structure. The architecture employs eight 1-D DCT processors and four post-addition stages to calculate two-dimensional DCT coefficients. Each 1-D DCT processor is designed using Algebraic Integer Encoding architecture which requires no multiplier, therefore...
An optimal architecture for decoding BCH code is presented in this paper. This design uses a new architecture for syndrome computation to avoid multiplication operation, a Modified Direct Solution Algorithm to reduce the time and area consumption, an inverse error locator polynomial to avoid inverse operation in Chien Search, a new architecture for Chien Search and Error Correction using Finite Field...
This paper proposes timing synchronization for IEEE 802.16e OFDMA downlink. The proposed scheme utilizes the conjugate symmetry property of preamble structure. Therefore, prior knowledge of actual transmitted preamble type is not required. Considering hardware complexity, this paper proposes a new single correlation function for 114 different structures of preamble in 802.16e OFDMA. As a consequence,...
This paper presents VLSI education system applied in under graduate and graduate program in Institut Teknologi Bandung. The program focuses on giving the ability to the students in designing a high performance integrated circuits (IC) using advanced EDA Tools. The VLSI education course covers from system architecture design up to IC physical design implementation. The contribution of research institutes,...
This paper explains a new design of a high speed MIPS (Microprocessor without Interlocked Pipelined Stages) based processor with significant improvements on instruction-level parallelism (ILP) and stall reduction to zero. These improvements are accomplished by utilizing four-stage pipelining, multiple-issue technique, and a Branch Target Buffer. The processor functionality has been verified on Altera...
Channel estimation is one of key problems in IEEE 802.16e Orthogonal Frequency Division Multiplexing Access (OFDMA) downlink system. Minimum Mean Square Error (MMSE) channel estimation has been known as a superior performance channel estimation. However, this algorithm has high computational complexity. In this paper, we present low complexity partial-sampled MMSE channel estimation for compromising...
In this paper, we present low complexity down-sampled MMSE channel estimation. We reduced MMSE channel estimation complexity by downsampling the MMSE weight matrix. The simulation results show that the bit error rate (BER) performance significantly improved over the least square channel estimation and has comparable BER performance with MMSE channel estimation at low SNR with significant decrease...
High mobility communication systems need suitable channel estimation to cope high frequency selectivity and time variation channel. In recent study on downlink OFDMA mobile WiMAX, channel estimation was done by exploiting pilot from preamble instead of pilot from data symbol due to ununiformly pilot spacing in this standard. In this paper we propose to obtain channel transfer function by exploiting...
This paper describes the design of a MIPS architecture with a small number of stall. Stall frequently happens in pipeline architecture which results in larger clock cycles. In this paper we significantly reduced stall by introducing pre-fetching unit. This unit reduces stall by concurrently reading three instructions and check their possibility of stall. If stall is detected, this unit then changes...
High mobility communication systems need suitable channel estimation to cope high frequency selectivity channel effect. In this paper we propose data pilot based channel estimation in downlink OFDMA for IEEE 802.16e standard (mobile WiMAX). The mobile WiMAX channel estimation can be done by exploiting pilot from preamble, in this paper we obtain channel transfer function by exploiting pilot at symbol...
This paper presents the design of synchronizer hardware for DVB-T receiver. The main function of synchronizer is to detect and compensate the time offset and frequency offset which happen during transmission as well as frame start detection. Proposed synchronizer utilizes cyclic prefix of OFDM signals. The design includes computational bit precision modeling, architecture design, register-transfer-level...
Here we present a new design of a 64-point fast Fourier transform circuit. The design is derived from Radix-23 algorithm and implemented using single path delay feedback architecture. This approach ensures high memory and multiplier utilizations. The 64-point FFT is realized by decomposing into two-dimensional structure of 8-point FFTs. Each of this FFT is re-decomposed into 4-point and 2-point FFTs...
In Digital Signal Processing, trigonometry and complex multiplications are used in many signal equations, such as synchronization and equalization. Therefore, a fast and an efficient method to calculate trigonometry and complex multiplications are required. Coordinate Rotation Digital Computer (CORDIC) is trigonometric algorithm that is used to transforming data from rectangular to polar and vice...
This paper describes architecture design for inverse-CABAC which is used for decoding entropy on H.264 decoder. The architecture design refer to JM 11.0 program in C language that was designed by Joint Video Team from MPEG and ITU. This reference program also produces test vectors as a reference input and output for verification purposes. The result of the inverse CABAC module proves that system functionality...
This paper present a design of RSA-encryption using Pipelined radix-2 Montgomery's architecture. The architecture design exploits the algorithm to achieve high speed and efficient computation. The design separates the computation of Montgomery modular multiplication into different clock cycles to achieve high frequency clock. This design supports input from 1 to 14 block data and efficient in the...
High mobility communication systems need suitable channel estimation to cope high frequency selectivity channel effect. In this paper we propose data pilot based channel estimation in downlink OFDMA for IEEE 802.16e standard (mobile WiMAX). The mobile WiMAX channel estimation can be done by exploiting pilot from preamble, in this paper we obtain channel transfer function by exploiting pilot at symbol...
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