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In this paper we describe and analyze the main features of the Hardware Real-Time Scheduler Coprocessor unit (HRTC) for NIOS II processor. We describe how the HRTSC supports time, events, task and priorities. The HRTSC was designed as a SOPC component to incorporate real-time features for embedded real-time applications. The hardware architecture has an easy integration with the IDE programming environment...
Real-time systems are used in control applications. However, real-time systems may introduce undesirable effects on the control application. Stability, overshoot and settling time are affected when an inadequate real-time system is used. The uRT51 is an embedded processor designed for real-time applications. In this paper we analyse the perturbations that the uRT51 produces on a control application...
In this paper we describe the design of a platform for experiments in the power quality area. The platform is intended for laboratory experiments as well as education on power quality methodologies and equipment. Nowadays, the power quality requires sophisticated approaches to get an efficient utilization of both: the electrical energy and the electrical installations and equipment. However, the real...
In this paper we propose a digital architecture to implement a PLL for a sinusoidal analog input. This kind of components is intended for synchronization between the voltage (current) of a AC power line and a voltage (current) synthesized by a converter. The architecture is based on binary-rate multiplers modules and generates the sine and the cosine values of the sinusoidal input reference. Most...
This paper presents an analysis of the Rate Monotonic scheduling of an 802.4 network operating in a hard real-time environment. The worst-case number of priority inversions is determined. With that, an iterative algorithm is derived to partition the set of nodes in priority classes and to assign the two fundamental medium access control parameters, Target Token Rotation Time and High Priority Token...
A heuristic approach to the problem of assigning a set of preemptible resource-sharing and blockable real-time tasks to be executed in a set of heterogeneous processors communicated through an interprocessor network, is presented. The problem is NP-hard. The empty-slots method is used to test the RM schedulability in each processor. There are placement, time, memory, communication and precedence constraints...
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