The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 800-MHz fractional-N PLL fabricated in a 0.18-μm CMOS process...
A multiplying-DLL-based frequency synthesizer with a fully integrated loop capacitor employs an adaptive current-adjusting loop to generate a low-jitter clock. The nonidealities in the general impedance converter (GIC) which is used as the loop capacitor are thoroughly discussed. Additionally, the discrete-time model for the clock generator with adaptive current tuning is presented and the analysis...
A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.
A 4.8GHz integer-N frequency synthesizer with distributed phase-frequency detectors and charge pumps moves spurious tones to higher frequencies and reduces the spur levels. PPM is used to relax the analog circuit accuracy requirement. The circuit is fabricated in a 0.18mum CMOS technology, dissipates 18mW from a 1.8V supply and suppresses sidebands by 10dB
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.