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This paper presents a method to salvage malfunctioned bits in a FinFET SRAM array caused by random threshold voltage (Vt) variation. The Vt of pass gates (PGs) is gradually lowered during the read process from the initial high value until the stored data is detected by the sense amplifier. As a result, the best Vt is automatically chosen for each cell and malfunctioned bits of both those too fast...
PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak...
Variability of the TiN FinFET SRAM cell performance is comprehensively studied. It is found that the static noise margin (SNM) variation of the SRAM cell is due to the Vth variation of FinFETs caused by the work function variation (WFV) of the TiN metal-gate. It is experimentally demonstrated that the Vth-controllable independent-double-gate (IDG) FinFET technology successfully compensates not only...
The area penalty, operation stability, and operation speed of the 20-nm-ZG FinFET SRAM were compared to those of the 20-nm-ZG bulk-planar SRAM. The FinFET SRAM with beta-ratio of 1 is expected to realize not only 7% less area penalty, but also the same or superior operational stability to that of the bulk-planar SRAM with beta-ratio of 2 because of less variability of the device performance. Also,...
FinFET performance variability is comprehensively investigated for undoped/doped channels with various gate materials. By evaluating the influence of channel doping, fluctuation of gate length and that of fin thickness, it is found that gate workfunction variation (WFV) is the dominant source of Vt variation for the undoped FinFET and that the WFV increases with scaling of gate area. In addition,...
An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new SRAM consists of IDG-FinFETs which have flexible Vth controllability. The IDG-FinFET with a TiN metal gate is fabricated by a newly developed gate-separation etching process. By appropriately controlling the Vth of the IDG-FinFET, we have successfully...
SRAM cells with Vth-controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated SRAM cell with various circuit topologies has been investigated comprehensively. Both a reduction of leakage current and an enhancement of read and write noise margins have been successfully demonstrated by introducing the IDG FinFETs into the SRAM cells.
We propose a flexible-pass-gate (Flex-PG) FinFET SRAM to enhance both the read and write noise margins. The flip-flop in the Flex-PG SRAM cell consists of usual FinFETs while its pass gates consist of Vth-controllable four-terminal (4T) FinFETs with independent double-gates. We experimentally demonstrate that the proposed Flex-PG SRAM increases both the read and write margins by controlling the Vth...
Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low-Vt CMOS FinFETs representing on-current enhancement and high-Vt CMOS FinFETs reducing stand-by power dramatically, namely multi-Vt CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with...
TiN gate FinFET SRAM half-cells with different ??-ratios from 1-3 have successfully been fabricated by using the orientation dependent wet etching and conventional reactive sputtering, for the first time. It is experimentally found that static noise margin (SNM)at read condition increases with increasing ??-ratio due to the strength of pull-down transistor. To overcome SRAM cell size increment with...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
We propose a flex-pass-gate SRAM (Flex-PG SRAM), i.e., a FinFET-based SRAM to enhance both the read and write static noise margins (SNMs) independently. The flip-flop in the Flex-PG SRAM consists of usual FinFETs while its pass gates consist of double-"independent"-gate FinFETs, four-terminal-FinFETs. A TCAD simulation revealed that the Flex-PG SRAM increases the read SNM by 70 mV even when...
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