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Software-defined radio (SDR) is a rapidly evolving technology. SDR have been widely studied as a solution to support multiple competing and in compatible air interface standard in future wireless communications. In this paper, we present the design of a digital down converter (DDC) module for triple-mode WCDMA, CDMA2000 and GSM. The designed module consists of digital mixer, CIC filter, and decimation...
Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array...
A vision of future wireless networks is the coexistence of multiple access network technologies. Different access networks will coexist and the Internet Protocol will be the joint layer. Controlling the resources of these networks is very challenging. This paper deals with two data oriented access networks, the worldwide interoperability for microwave access (WiMAX) and the high speed downlink packet...
The term software defined radio (SDR) is usually used to refer to a radio transceiver in which its key parameters are defined in software and having its fundamental aspects reconfigurable by upgrading that software. SDR architecture has been proposed as a solution to support multiple wireless standards on a single platform. In this paper, we present the architecture of an all-digital transmitter with...
The front-end digital encoder has become the bottleneck of the ultra-high speed flash ADCs. Pipelined digital encoder suites for 4-bit ultra high speed flash ADC is presented in this paper. It has two-stage pipelining to enhance the speed. The design is simulated and implemented using 0.18 mum UMC CMOS technology. The proposed encoder operates with 2.5 GSPS and consumes 0.8 mW. The proposed encoder...
Software defined radio (SDR) is a rapidly evolving technology that is receiving enormous recognition and generating widespread interest in the telecommunication industry. In this paper, we present the architecture of an all-digital transmitter with radio frequency output targeting FPGA devices due to their reconfigurability and programmability. The all-digital transmitter directly synthesizes RF signal...
One channel of 4 bit high speed flash ADC using a 0.18 mum CMOS technology is reported. This is part of 4 channel time interleaving ADC. The design is preceded by a differential S&H circuit which operates on 1.5 GS/s. This system is suitable for very high speed application.
This paper presents a four-bit flash type Analog to Digital Converter (ADC). The design is suitable for Ultra Wide Band (UWB) applications due to its high operating frequency and low power consumption. The high operating frequency is due to the pipelined nature of the design. The low power consumption is due to the minimized transistor sizes and modularity of the design. The proposed ADC is designed,...
In this paper a novel design of an 11 bit digital-to-analog converter (DAC) is introduced. The design is to be integrated in a direct digital frequency synthesizer (DDKS). The designing of a DAC is critical due to its poor performance and low speed. The proposed design consists of three modules, a linear DAC, a nonlinear DAC and a nonlinear interpolation DAC. Each module contributes in enhancing the...
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