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This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches' constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s...
A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance...
A kind of power conversion circuit, which converts positive voltage into negative one is presented according to the principle of negative voltage charge pump, so the DC output voltage is doubled. Factors affecting the speed and accuracy of MOS switches are fully considered, and a charge pump with MOS switches working in linear region is designed, avoiding the problem of threshold voltage drop. By...
A low power consumption, high speed op-amp is designed for a 10-bit, 100 MSPS parallel pipeline A/D converter. The op-amp plays an important role in the ADC, because its conversion rate and power consumption are limited by the performance of the op-amps. The designed ADC in this paper employs parallel architecture based on double sampling technology, and shares the op-amp between the same stages of...
Based on analyzing of the influence of the current switch driver on dynamic performance of the high-speed current-steering DAC, several key points of designing the current switch driver are proposed. The low cross-point method, synchronous flip-latch and limited swing of switch driver are introduced, and a current switch driver circuit is proposed. In order to further improve the dynamic performance...
A 14-bit, 130MSPS DAC with 2times FIR interpolation filter simulated in a 0.35 mum CMOS process is described in this paper. The DAC adopts segmented current-steering structure, which combines the characteristic of unit current DAC and the binary weighted DAC to get the balance between area and performance. A 2times FIR interpolation filter is introduced to reduce the complexity of analog reconstruction...
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