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We have applied thoroughly clock gating technique to the SH-4A FPU (Floating Point Unit) core [1] while still keeping it co-operates with CPU core. As a result, 97% flip-flops in FPU is gated. And the power consumption is saved up to 78.11% in FPU, corresponding to 17.02% power consumption reducing of total CPU and FPU core in Dhrystone benchmark. This paper introduces such approach in which the clock...
Instruction set development is an effective way to improve processor performance. In SH-4A core enhancement, Prefix instruction is introduced as a technique to enrich function of original instruction. As a result, we have successfully integrated 130 new 32-bit instructions to 16-bit original instruction set and performance of new core is improved up to 43% compared to conventional model.
We have developed a platform SoC including eight SuperH processor cores for high performance applications. It achieves 8,640 MIPS at 600 MHz for Dhrystone 2.1. The eight processor cores are divided into two clusters. Each cluster has a snoop controller to maintain cache coherency. The main internal system bus, packet-based split transaction, is 64 bits wide and runs at 300 MHz. As increasing number...
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