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This paper presents a wideband, direct-conversion radio receiver front-end that targets all WiMAX/WLAN bands from 2.3-GHz to 5.8-GHz. The receiver front-end is fabricated in 0.18-μm CMOS and achieves a gain of 25 dB, noise figure of 6 dB, and IIP3 of -6 dBm while dissipating 28 mW from a 1.8-V power supply. This performance is achieved while using only two integrated inductors.
The IIP2 requirement in fully integrated direct-conversion receivers using FDD duplexing is prohibitively high and demands the use of an external filter in order to attenuate the leakage from the transmitter. This paper presents a digital calibration technique for passive CMOS down-converters that allows a direct conversion receiver achieve the requirements without external filtering. A Least-Mean-Square...
In this paper a low-power design of an integrated RF receiver for Wireless Sensor Networks (WSNs) in 90 nm CMOS technology is proposed. The receiver is IEEE 802.15.4 physical specifications compliant. It is designed to operate in ISM band at 2.45 GHz center frequency. Target devices for this kind of transceiver are low-cost battery powered smart embedded devices and sensors. The receiver is designed...
This paper presents the design challenges and solutions for 4 G nanometer radio receivers for mobile devices. The specifications for the ZERO-IF/LOW-IF 4 G receiver architecture are derived. Limitations due to the use of low-voltage nanometer technologies are described and novel circuit technique mobile systems, such as wideband noise reduction, inductor-less peaking, passive mixing, and low flicker...
RFIC design using low-voltage nanometer CMOS technologies offers both advantages and challenges. This paper describes the limitations of using these technologies in receiver front-end design and proposes circuit solutions. Several techniques such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are reviewed and employed. A receiver front-end that...
This paper presents a fully integrated receiver front-end for a 2.4 GHz RF transceiver. A system level design for the radio front end for which these components are designed is also presented. The proposed receiver front end (Low-Noise Amplifier, Single-to-Differential Converter and Mixer) is based on a direct conversion architecture designed in 0.18 mum CMOS technology. It takes advantage of on-chip...
Convergence into 4G wireless communication systems pushes the design of radio receivers beyond limits unconceivable only few years ago. The complexity of RF systems has increased enormously as new communication standards have appeared in the wireless scenario. The convergence trends, enabled by the advances in fabrication technology, have driven the software defined radio (SDR) more and more into...
This paper presents the systematic design of a 5-bit, 1.2 GSPS interpolative flash ADC for multiband OFDM UWB applications. The proposed ADC architecture employs the proven capacitive interpolation, which greatly reduce the power consumption, by eliminating the need of a power hungry resistive ladder. The flash ADC has been implemented in a 0.18 mum CMOS process. Circuit level simulations show that...
In this paper we show how TACT, a recently reported radio system design and optimization tool, can be used to optimize the design of a dual mode WCDMA/WLAN receiver. An overview of the underlying frequency planning and receiver budget analysis routines is discussed first. In a case study, a zero-IF WLAN/WCDMA radio receiver is then designed and optimized using the tool. TACT yields optimized design...
This paper addresses the different issues in the design of ADCs for future wireless handhelds. It reviews the constraints imposed on the receiver design by the low-power specifications in handhelds. The sigma-delta ADC architectures that can potentially be used for implementing future wireless handhelds are discussed in the perspective of a CMOS implementation. Finally, a 4th order 4bit continuous-time...
This paper presents the design methodology and underlying algorithms of a tool developed for automated receiver design and optimization for fourth generation (4G) wireless communication systems. An algorithm to systematically design and optimize the receiver budget for the multi-standard case is introduced. The goal of this algorithm is to find a multi-standard receiver budget that meets or exceeds...
A reconfigurable ADC based on a 2-2 modified cascaded SigmaDelta modulator designed for a GSM/WCDMA/WLAN/WiMAX zero-IF receiver has been presented. Employing the second-order feedforward SigmaDelta modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth is achieved. The P-DWA technique is applied in the first feedback 4-b DAC to eliminate the...
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