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This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve...
Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm times 10 mm times 0.4 mm and solder ball pitch of 0.4 mm. As part of the work several key processes like thin...
This paper focused on design, assembly and reliability assessments of 21 ?? 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ??m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97...
To study the effect of back grinding on the mechanical properties of the active side of the die, low-k stacked wafers were grinded to four different thicknesses of 500 mum, 300 mum, 150 mum, and 75 mum by using a commercial grinding process. Nanoindentation and nanoscratch tests were performed using the Nanoindenter XP (MTS Corp. USA) on both the normal (no back grinding) and back grinded samples...
This paper presents the study on the effect of low k stacked layer, chip pad design structures, and shift pad design TM of a large die size Cu/low kappa (BDtrade) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip ball grid array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported...
The mechanical strength of the low-k dielectric thin films plays vital role in deciding the integrity and reliability of the interconnect structures and Cu/low-k packages. Present study focuses on the thickness dependence of mechanical behavior of BD (low-k, Black Diamondtrade) thin films of four different thicknesses, 100, 300, 500 and 700 nm. Nanoindentation and nanoscratch tests have been carried...
The Sn–Ag/Au/Ni–P/Cu, Sn–Ag–Bi/Au/Ni–P/Cu, and Sn–Ag–Cu/Au/Ni–P/Cu diffusion couples were prepared by reflowing the Pb free solders on the top surface metallization of the substrate at 250 °C. They were annealed at 150 and 170 °C for 4, 8, 16, 36, 45 days. The surface morphological features of intermetallic compounds (IMC) formed among the different elements in the solder alloys were characterized...
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