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In the era of terascale integration, the “reliability wall” and the “power wall” arise as barriers imposing significant challenges to the microprocessor industry. Nowadays, on-line testing is essential for modern microprocessors to detect latent defects that either escaped manufacturing testing or appear during system operation. Moreover, many-core scaling is now facing the “power wall”. More cores...
For small memory arrays that usually lack Memory Built-In Self-Test (MBIST), such as Translation Lookaside Buffer (TLB) arrays, Software-Based Self-Test (SBST) can be a flexible and low-cost solution for on-line March test application. In this paper, an SBST program development methodology is proposed for on-line testing of data TLB (D-TLB), both for data (SRAM) and tag (CAM) memory arrays. The SBST...
Nowadays, on-line testing is essential for modern high-density microprocessors to detect either latent hardware defects or new defects appearing during lifetime both in logic and memory modules. For cache arrays, the flexibility to apply online different March tests is a critical requirement. For small memory arrays that may lack programmable Memory Built-In Self-Test (MBIST) circuitry, such as L1...
Wireless Sensor Network (WSN) applications often need to be deployed in harsh environments, where the possibility of faults due to environmental hazards is significantly increased, while silicon aging and wearout effects are also exacerbated. For such applications, periodic on-line testing of the WSN nodes is an important step towards correctness of operation. However, on-line testing of processors...
Software-Based Self-Test (SBST) has emerged as an effective method for on-line testing of processors integrated in non safety-critical systems. However, especially for multi-core processors, the notion of dependability encompasses not only high quality on-line tests with minimum performance overhead but also methods for preventing the generation of excessive power and heat that exacerbate silicon...
Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in-system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March test application and thus a viable supplement to hardware approaches. In this paper, a generic SBST program development methodology is proposed for...
Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical applications. Among the various systems that fall in the previous category, wireless sensor networks (WSN) are often deployed in harsh environments where the possibility of permanent and especially intermittent faults due to environmental hazards is significantly...
Software-based self-test (SBST) has emerged as an effective strategy for non-concurrent on-line testing of processors integrated in embedded system applications. It offers the potential for on-line testing without any hardware overhead. However, test generation is usually based in a semi-automated approach and gate-level information is required for effective test program generation.In this paper we...
In this article, we introduce a hybrid-SBST methodology for efficient testing of commercial processor cores that effectively uses the advantages of various SBST methodologies. Self-test programs based on deterministic structural SBST methodologies combined with verification-based self-test code development and directed RTPG constitute a very effective H-SBST test strategy. The proposed methodology...
Software-based self-test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the most popular applications falling in this category are the various mobile devices. However, in-field testing of processors integrated in mobile devices has the extra requirement of minimum energy consumption, since these devices...
In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We propose a method for significantly reducing the fault list by removing the faults on unused LUT bit positions. We also target the design flip-flops...
Today's nanometer technology trends have a very negative impact on the reliability of semiconductor products. Intermittent faults constitute the largest part of reliability failures that are manifested in the field during the semiconductor product operation. Since software-based self-test (SBST) has been proposed as an effective strategy for on-line testing of processors integrated in non-safety critical...
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