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In this paper, a 2.5-Gb/s oversampling clock and data recovery (CDR) circuit with frequency calibration is realized for optical communication. The CDR circuit contains a fractional-N phase-locked loop (PLL), a delta-sigma modulator (DSM) and a data recovery circuit. The recovered clock is adjusted by the DSM for phase and frequency tuning, incorporating with the phase detector, when the incoming data...
In this paper, a burst-mode clock and data recovery (CDR) circuit using a half-rate clock technique is realized for optical communication. The CDR circuit contains a frequency detector and a data-injection oscillator to control the frequency of the recovered clock. In-lock operation can be accomplished on the first data transition, and then the output clock is in phase for all data until the data...
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