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We propose an approach to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints...
A new approach is proposed for evaluating circuit robustness against Single Event Transients (SETs) through FPGA emulation. A voltage-time quantization model allows capturing circuit delays in the FPGA, including electrical masking effects. Experimental results demonstrate this approach improves SET fault injection rate by three orders of magnitude with respect to logic simulation and provides an...
Single event transient (SET) fault analysis is usually performed trough digital simulation at the gate level. However, this method cannot be used for large fault injection campaigns, since gate level simulation is quite slow. In this paper, we propose an approach to build an FPGA based SET emulator, which implements a quantized delay model of the circuit under evaluation. Experimental results demonstrate...
The environment can produce transient faults in digital circuits, especially nowadays with the new technology development. Fault injection has been widely used to evaluate the hardness degree of circuits in which fault tolerance is a requirement, like aerospace or automotive applications. The magnitude of the fault effects evaluation problem is computationally unaffordable, if an exhaustive test must...
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