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This paper presents the fixed and floating point implementations for field-programmable gate arrays (FPGA) of third-order hand tremor predictors using recursive-least square (RLS) and a proposed Kalman adaptation algorithms. The proposed algorithm outperforms RLS in convergence speed and mean square error (MSE). It also shows better numerical convergence than the RLS as the number of bits in fixed-point...
This paper presents the design of a 1 Gb/s 5-tap T/2 fractionally-spaced equalizer. The T/2 delay lines are based on third-order linear-phase double terminated sections that offer a tunable group delay of 500 ps with less than 10% ripple and a 3 dB bandwidth greater than 600 MHz. Furthermore, the equalizer architecture introduces a broadband summing circuit using a transimpedance I/V converter that...
The 5-tap FIR structure uses 3rd-order linear-phase cells to implement delays of 500ps for a T/2 fractionally-spaced equalizer. To improve the bandwidth of the summing circuit, the design incorporates a transimpedance load, increasing the bandwidth by a factor of 3.6 over a conventional resistive load. The equalizer consumes 96mW with plusmn1.5V and occupies 0.26mm2 in a CMOS 0.35mum process.
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