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As transistor density grows, increasingly complex hardware designs may be implemented. In order to manage this complexity, hardware design can be performed at a higher level of abstraction. High level synthesis enables the automatic conversion of algorithms into hardware implementations, abstracting away the underlying complexities of hardware from the designer. A number of high level synthesis tools...
Linear systems with Toeplitz coefficient matrices often appear in applied science problems. Systems of this form arise as a result of finite difference methods when applied to approximate differential equations with boundary conditions. The sparse structure of Toeplitz matrices lend themselves well to iterative algorithms, such as projection methods, and are favored techniques for solving large systems...
Utilizing high level hardware description languages for the creation of customized circuits facilitates the rapid development and deployment of new hardware. While hardware design languages increase the speed at which hardware can be developed, creating hardware designs that are both efficient in resource usage and processing speed can be time consuming and require much experience. This problem is...
Reconfigurable hardware has recently shown itself to be an appropriate solution to speeding up problems that are highly dependent on a particular complex or repetitive sub-algorithm. In most cases, these types of solutions lend themselves well to parallel solutions. The optimal design on field programmable gate arrays (FPGAs) for problems with algorithms or sub-algorithms that can be highly parallelised...
High level hardware design languages are making it possible for people with little background in hardware design to create their own custom hardware. This allows software designers to begin looking beyond general purpose computing into the realm of customized hardware in order to increase the performance of their applications. The ease with which hardware can be developed using hardware definition...
Computing the irreducible and primitive polynomials under GF(3) is a computationally intensive task. A hardware implementation of this algorithm should prove to increase performance, reducing the time needed to perform the computation. Previous work explored the viability of a co-designed approach to this problem and this work continues addressing the problem by moving the entire algorithm into hardware...
Speed and security of data streams are two key factors in different areas such as data communication and multimedia. Compression algorithms are applied to data streams to increase their communication speed while encryption algorithms are used for assuring the security of the data transfer. AES and LZ77 are two well known algorithms for data encryption and compression respectively. In this paper we...
The widespread availability of field programmable gate arrays (FPGA) coupled with different implementations of "soft-core" processors has created a need to find new methods for optimizing these processors. Because design space is limited on most FPGA's and the maximum clock rate of these processors is heavily bound to the overall size and resource usage it is necessary to find ways to minimize...
This paper presents an implementation of the interface of a co-designed virtual machine. It introduces the concept of a co-designed virtual machine, describes the communication requirements of the interface and explains how using a System-on-Chip design can improve the performance of the co-design system. A general model for the communication between hardware and software is presented, and results...
Embedded system applications in commercial products are quickly taking precedent as the ideal solution addressing the consumer push for smaller, more robust, low cost devices. Bearing this, it is essential that we as students of the technology acknowledge this demand for heterogeneous appliance, and adopt the practice of developing co-dependent applications. As it stands, commercially available development...
In previous research, a novel structure was discussed for representing the matrices that can be built from an n-variable r-valued reversible/quantum circuit. This structure, called a QMDD, takes on a form similar to that of a reduced-ordered-binary-decision-diagram (ROBDD). It is known that the order of variables used for developing an ROBDD from a binary logic circuit is relevant to the size and...
The common language infrastructure (CLI) provides a framework for managing and executing applications. Developers designing applications for the CLI need not worry about the underlying architecture as it is abstracted from view by the CLI framework. This abstraction, while a boon for developers, leads to degraded performance. It is because of these inefficiencies that the CLI is not well suited for...
A reprogrammable hardware platform is used for the co-design and implementation of a computational intensive mathematical problem, namely the listing of irreducible polynomials over Galois fields of order 3 (GF(3)), The main goal is to accelerate the performance compared to an existing software implementation. This project uses hardware/software co-design methodologies and techniques, and it is completely...
A new technique that makes use of a systolic array structure is proposed for solving the common approximate substring (CAS) problem. This approach extends the technique introduced in (Kent et al., 2006) from the computation of the edit-distance between two strings to the more encompassing CAS problem. The technique presented is validated and analyzed through simulation
Biologists require ways to rapidly sequence vast amounts of DNA information. An approach to satisfying the demand is to provide hardware support and leverage parallel computation. When providing hardware acceleration it is known that a custom specific circuit would provide a high performance solution. Providing a balance between delivering an application-specific circuit while achieving optimal utilization...
Virtual machine technology allows for the reuse of applications and code over various heterogeneous platforms. A virtual machine simply adds another layer of abstraction between the application and the native hardware. A major drawback of an application running on a virtual machine, however, is that the performance is below that of an application targeted for a native platform. Previous work has dealt...
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