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Technology scaling and large-scale integration make the operating environment increasingly hostile for traditional analog design. In the area of frequency synthesis, All-Digital PLLs (ADPLLs) provide an attractive alternative to conventional PLLs: their wide programmability allows for multistandard application, and a digital intensive design means easy reconfigurability and shorter design cycles....
Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming...
A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the...
A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13mum CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dBof -31dBm
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