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We have fabricated InP SOAs with lithographically-defined etched facets. Their more precisely-controlled length compared to cleaved SOAs promises improved coupling tolerances for PICs with flip-chip attached gain blocks. Measured gain is around 20dB and noise figures are 5–6dB.
A DC-coupled burst-mode receiver performs optical power calibration in 12.5ns, achieves phase lock in 18.5ns and tracks input data using a CDR. The sensitivity of the 4.4pJ/bit receiver is −10.9dBm (BER < 10−12) at 25Gb/s.
A novel high-speed Mach-Zehnder modulator (MZM) fully integrated into a 90 nm CMOS process is presented. The MZM features ‘double-pass’ optical phase shifter segments, and the first use of integrated inductors in a ‘velocity-matched’ distributed-electrode configuration.
A monolithically-integrated germanium receiver is fabricated in the IBM's newly established 90nm CMOS-integrated nanophotonics technology node. Technology is promising for cost-effective 10Gbps to 28Gbps optical communications links operating within extended temperature range up to 95°C.
The emerging field of silicon photonics targets monolithic integration of optical components in the CMOS process, potentially enabling high bandwidth, high density interconnects with dramatically reduced cost and power dissipation. A broadband photonic switch is a key component of reconfigurable networks which retain data in the optical domain, thus bypassing the latency, bandwidth and power overheads...
CMOS Integrated Nanophotonics allows ultra-dense monolithic single-chip integration of optical and electrical functions. This technology can enable future Exaflops supercomputers by connecting racks, modules, and chips together with ultra-low power massively parallel optical interconnects.
We review results on design and development of 4×4 silicon nanophotonic non-blocking switch arrays integrated with driving analog CMOS circuits for circuit-switched optical networks. Such high-radix optical routers are envisioned for future Exascale computer systems.
In the last 10 years interconnects in many high performance servers and supercomputers transitioned from copper interconnects to optical interconnects. In this presentation a technological roadmap towards will be reviewed, focusing on the evolution of interconnect power and density efficiencies.
A single-chip CMOS parallel optical transceiver, or Optochip, is presented that addresses the key metrics of power consumption, density, bandwidth, and cost, to enable large-scale parallel optical links through fiber or waveguide-arrays.
We demonstrate a low power optical interconnect transmitter which employs a 990 nm VCSEL with high efficiency and low threshold current, and a 130 nm CMOS driver. The power dissipated by the transmitter is 15.1 mW at 10 Gbps.
We review architectures enabling >100 Gb/s interconnects in data centers. Parallel optical interconnects are cost effective for rack to rack interconnects. On-board optical waveguides offer data rate scalability, density and performance advantages over electrical interconnects.
We demonstrate a 17 Gb/s optical link using transmitter and receiver CMOS integrated circuits. We achieved error free operation over a 200-meter long OM3 multimode fiber operating at 850 nm
We report three different optical receivers, consisting of Ge photodiodes paired with CMOS ICs, that operate at bit rates as high as 19 Gb/s and consume as little as 1.1 mW/Gbps from a single 1.1-V supply at 10 Gb/s
Terabus is based on a chip-like optoelectronic packaging structure (Optochip) assembled directly onto an organic card with integrated waveguides (Optocard). To-date, Terabus has demonstrated 4times12-array optical transmitters and receivers operating up to 20 Gb/s and 14 Gb/s per channel
We report on a sampled grating DBR laser monolithically integrated with a Mach-Zehnder modulator and a semiconductor optical amplifier. Transmission over 100 km of standard fiber at 10 Gb/s is demonstrated across 30 nm tuning range.
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