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The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with...
Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced...
The optical properties (complex dielectric function) and critical-point parameters for Si1-yCy alloys with high substitutional C content grown pseudomorphically on Si (001) were determined. These data are useful for process control (if such alloys are used in CMOS processing), for example using spectroscopic ellipsometry to determine film thickness, modulation spectroscopy (especially photoreflectance)...
This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum...
This paper describes the novel stress engineering of SC-SSOI devices through the interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation. We have demonstrated a method of uniaxial stress relaxation with compressive capping layer (cESL) to achieve the desired stress configurations for enhanced short-channel SC-SSOIpMOS devices
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