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Notice of Violation of IEEE Publication Principles??A Single-chip Digitally Enhanced Radio Receiver for DBS Satellite TV Applications??by A. Maxim, R. Poorfard, R. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, D. Trager, M. Reidin the Proceedings of the 2008 IEEE Radio and Wireless Symposium,Page(s):787-790After careful and considered review, it has been determined that the above paper is in violation...
Notice of Violation of IEEE Publication Principles??A 0.13 ??m CMOS DBS Demodulator Front-end Using a 250MS/s 8 bit Time Interleaved Pipeline ADC??by A. Maxim, R. Poorfard, M. Chennamin the Proceedings of the 2008 IEEE Radio and Wireless Symposium,Page(s):53-56After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.Specifically,...
Notice of Violation of IEEE Publication Principles??A 10GHz Low Phase Noise 0.13??m CMOS LC-VCO for Mixed Signal SoCs Using Noise Rejection Caged Inductors??by A. Maxim,in the Proceedings of the Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 IEEE3-5 June 2007 Page(s):693-696 After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication...
Notice of Violation of IEEE Publication Principles??0.13???? CMOS Hybrid TV Tuner Using a Calibrated Image and Harmonic Rejection Mixer??by Maxim, A.; Johns, R.; Dupue, S.;in the Proceedings of the 2007 IEEE Symposium on VLSI Circuits,14-16 June 2007 Page(s):206 - 207After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication PrinciplesSpecifically,...
Notice of Violation of IEEE Publication Principles"Fully-Integrated 0.13 μm CMOS Digital Low-IF DVB-S S2 Satellite TV Tuner Using a Discrete-Step AGC Loop"by Maxim, A.; Poorfard, R.; Johnson, R.; Crawley, P.; Kao, J.; Dong, Z.; Chennam, M.; Nutt, T.; Trager, D.;in the Proceedings of the 2007 IEEE Radio and Wireless Symposium,Jan. 2007 Page(s):67 - 70After careful and considered review, it...
Notice of Violation of IEEE Publication Principles"A -5OdBc Spur 0.13 μm CMOS Ring Oscillator PLL for DBS Satellite Receiver SOCs Using a Multi-Regulator Architecture"by Maxim, A.; Poorfard, R.; Kao, J.;in the Proceedings of the 2007 IEEE Radio and Wireless Symposium,Jan. 2007 Page(s):427-430After careful and considered review, it has been determined that the above paper is in violation...
Notice of Violation of IEEE Publication Principles??A Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged Inductors??by Maxim, A.in the Proceedings of the IEEE Custom Integrated Circuits Conference 2006,10-13 Sept. 2006 Page(s):663 - 670After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles...
Notice of Violation of IEEE Publication Principles"A -85dBc Reference Spurs Quadratude 1-2.5GHz Dual-Path Sampled Loop Filter CMOS PLL with sub-1??rms Phase Noise"by Maxim, A.; Gheorghe, M.;in the 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. San Francisco, CA, 2006After careful and considered review, it has been determined that the above paper is in violation of IEEE's...
A fully integrated 0.13mum CMOS ring-oscillator-based PLL for low-IF single-chip DBS satellite tuner-demodulator IC is presented. A noise-attenuating loop filter reduces the oscillator gain, helping both front-end noise and spur rejection and allowing the on-chip integration of the filter capacitance. The PLL shows <1.5degrms double-sided integrated phase noise, <-60dBc reference spurs, <-50dBc...
A first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wide bandwidth, ring oscillator integer-N frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to base band was performed in the digital domain. Eliminating the oscillator inductors...
The first low-IF fully-integrated tuner for DBS satellite TV applications was realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to down-convert a cluster of channels to a coarsely defined low-IF frequency, while the second down-conversion to baseband was performed in the digital domain. Eliminating the oscillator inductors has...
Notice of Violation of IEEE Publication Principles??A 9.953/10.7/12.5 GHz 0.13 ??m CMOS LC oscillator using capacitor calibration and a VGs/R based low noise regulator??by Maxim, A.in the Proceedings of the 2005 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers.12-14 June 2005 Page(s):411 - 414After careful and considered review, it has been determined that the above paper...
Notice of Violation of IEEE Publication Principles??A -86dBc reference spurs 1-5GHz 0.13 ??m CMOS PLL using a dual-path sampled loop filter architecture??by Maxim, A.in the Proceedings of the 2005 Symposium on VLSI Circuits, Digest of Technical Papers.16-18 June 2005 Page(s):248 - 251After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication...
Notice of Violation of IEEE Publication Principles"9.953-12.5GHz 0.13??m CMOS LC VCO Using a High Resolution Calibration and a Constant Gain Varactor"by A. Maxim and C. Turinici,in the Proceedings of the IEEE Custom Integrated Circuits Conference, 2005After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.Specifically,...
Notice of Violation of IEEE Publication Principles??A sub-Ips rms jitter 1-5GHz 0.13??m CMOS PLL Using a Passive Feedforward Loop Filter with Noiseless Resistor Multiplication??by Maxim, A.; Gheorghe, M.in the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2005. Digest of Papers.After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication...
Notice of Violation of IEEE Publication Principles??A 2-5GHz low jitter 0.13 ??m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]??by Maxim, A.in the Proceedings of the IEEE 2004 Custom Integrated Circuits Conference,3-6 Oct. 2004 Page(s): 147 - 150After careful and considered review, it has been determined that the above...
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