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The effects of the diffusion control technique by inserting physical vapor deposition (PVD)-TiN film between poly-Si and CVD-TiN films on the properties of p-MISFETs using poly-Si/TiN/HfSiON gate stacks have been studied. This insertion was effective in suppressing the diffusion of Si from poly-Si to HfSiON and was able to reduce the Vth value by 0.12 V while keeping the equivalent oxide thickness...
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability....
In this paper, the authors demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower Vth in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation Vth lowering up to ~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated...
High performance Ni-FUSI/HfSiON CMIS with suitable Vth in a wide Lg range is presented. This is accomplished by ion implantation to substrate and phase control of Ni-FUSI gate. Threshold voltage of NiSi-FUSI NMIS is controlled by nitrogen implantation, and that of Ni2Si-FUSI PMIS is controlled by fluorine implantation. It is demonstrated that N/F incorporation can realize 0.2-V-low |Vth|, high carrier...
A simple high-k/poly-Si dual-gate CMIS platform with a novel method to control threshold voltage (Vth) has been proposed for 45nm node. The PMIS Vth control method is a simple selective fluorine-implantation to channel region with optimizing extension and pocket implantation. We have also demonstrated the transistor variability improvement with our HfSiON/poly-Si platform, compared to SiON/poly-Si...
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