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A 4-Mb SRAM with 15-ns access time and selectable (*4/*1) bit organization based on a 0.55- mu m triple-polysilicon double-metal CMOS technology is discussed. To achieve 15-ns access time, a sense amplifier with input-controlled PMOS loads (ICPLs), Y-controlled bit line loads, and transfer word driver are used. A built-in voltage regulator is provided to reduce the internal supply voltage to 4 V....