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The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the Ion-Ioff relation. A modification of the linear piezo model is presented to simulate the hole...
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for...
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