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Slowing Moore's law and never-ending system demand for multi-functional integration had set a new stage for “advanced packages”, since 2.5D interposer FCBGA with GPU & HBM successfully developed in 2015. Recently “Fan Out Wafer-level Package” started to be adopted by high-end smart phone AP design, for ultra-thin and excellent interconnect performance. This not only inspires packaging industry,...
Semi-Additive Process (SAP) had been used for making fine line/space organic substrate for decades. As the line/space trends down to below 10um/10um, there are many difficult process challenges such as the uneven substrate surface across large area of say 500mm×400mm for process tool with a small depth of focus to cover, and the process uniformity control for plating thickness, regardless of the high...
Coreless embedded trace has attracted interest from mobile device, in few metal layer Flip-Chip Chip Scale Package (FCCSP) substrate design, for electrical performance, high density, and thickness reduction. However, the mainstream Prepreg (PP) dielectrics with glass-cloth utilized in coreless embedded trace substrate (ETS) are insufficient to fulfill future requirements of warpage behavior, RF performance,...
Flip-Chip Chip-Scale Packaging (FCCSP) has recently emerged as one of mainstream package solutions due to the superior performance & miniaturization over the wire-bonding technology. There had been lots of efforts to enhance the assembly process efficiency and therefore cost effectiveness. We propose an innovative heterogeneous process integration of the organic substrate and the standard FCCSP...
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