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Wireless sensor networks (WSNs) include a large number of distributed sensor nodes that consist of sensor, microcontroller and transceiver block. As the main source of energy sensor nodes usually use non-rechargeable batteries, so that the stored energy is a very important resource of a WSN. The main goal of this paper is estimating the battery lifetime of a sensor node in respect to the usage pattern...
Sensor networks usually complete several data processing tasks that include the acquiring sensor samples, preparing messages containing data, and sending/receiving radio messages. In this paper, we consider the impact of the sensing subsystem, intended for area monitoring applications, and its effect on the power consumption of sensor networks. We describe a sensing subsystem with implemented power...
Multi-year operation on a single coin-cell battery in sensor nodes is a crucial issue for energy efficiency Wireless Sensor Networks. Several methods to solve this problem have been applied. In our solution, we use one simple, but efficient technique, named modified rendezvous scheme with resizable guard selection. With aim to achieve correct in-time wake-up of SNs, we have implemented some modification...
The article describes a Fault-Tolerant Reconfigurable Low-power pseudoRandom number Generator (FT_RLRG) which integrates both Fibonacci and Galois LFSRs into a single hardware core. The design of FT_RLRG is of practical interest in testing triple modular fault-tolerant systems in the presence of single event upsets (SEUs), especially in case when the system is SRAM based. The main idea is to design...
As CMOS technology has scaled, supply voltage has dropped, chip power consumption has increased, and clock frequency has increased, the effects of jitter become critical and jitter budget gets tighter. Jitter can be decomposed into several components, each having specific sets of characteristics and root causes. This paper presents a short review of jitter fundamentals including a discussion of the...
Performance and fault tolerance, FT, are two dominant issues during development of complex real-time embedded systems, RT_ES. FT is generally accomplished by using redundancy in hardware, software, time, or combination thereof. Triple modular redundancy, TMR, is one of the most popular FT hardware scheme which uses spatial redundancy. In this paper a design of FT psedorandom generator, FT_PRNG, based...
In this paper has been presented the way of design and implementation of WirelessHart in the work with the modified TrueTime simulator based on the MATLAB/Simulink, which can simulate the regulating and control mechanism in the execution of tasks in real-time systems, networks and dynamic plants. WirelessHart MAC protocol has been designed and implemented with some C++ functions with the suitable...
In this paper, we have presented a phase loop for controlling a chain of gm-C all-pass filters. It's called Delay Locked Loop for Analog Signal Processing, and it's used for signal's phase regulation. 0.35 ??m CMOS technology was used for design and verification of the circuit. According to the obtained results, we have concluded that it is possible to obtain a phase regulation in a wide frequency...
The need for an efficient interconnect architecture has been caused by continued increase of the required communication bandwidth and concurrency of small-scale digital systems. The issue of applying the code division multiple access (CDMA) technique for data transfer over peripheral bus are discussed in this paper. The proposed technique represents an efficient interconnection solution for implementation...
In high-speed CMOS clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer (Fenghao and Svensson, 2000). In this paper, we propose a pulsewidth control loop referred as APWCL (adaptive pulsewidth control loop) that adopts the same architecture as the conventional PWCL, but with two modifications. The first one relates to implementation...
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