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Cost remains a key factor for implementation of Through Silicon Via (TSV) in high-volume manufacturing. As compared to via-first and via-middle TSV, via-last (from wafer back-side) TSV possesses the advantage of a more simple process flow and more flexibility in integration for more varied applications. Previously, a cost model analysis for Through-Silicon-Interposer (TSI) using via-first TSV has...
Microstructure analysis plays an important role in the reliability study of copper Through-Silicon Vias (TSVs). While conventional 2-dimensional (2D) Electron Back-Scatter Diffraction (EBSD) is a useful technique, 3-dimensional (3D) EBSD characterization provides a more accurate picture of the TSV microstructure. Information that is missing in 2D observations, such as grain shape and volume, can be...
Copper Through-Silicon Via (Cu TSV) is becoming a key technology for three dimensional (3D) packaging and 3D integrated circuit (IC) applications. The microstructure of the Cu TSV is important as it not only affects the electrical properties, but ma y play a role in its reliability such as protrusion. In this study, physical vapor deposition (PVD) and electroplated (ECP) Cu TSV microstructure evolution...
For MEMs application, we developed dense TSV coils and stacking technology. The dense TSV coils (20um width, 10um space, 90um depth) were void-free filling by Cu. 8 chips stacking with dense coils are demonstrated by conductive adhesive. The resistance, inductance and magnetic field of 8 stacked dense coils are characterized and reported in this paper.
RDL process becomes more and more important with through Si interposer (TSI) application in 3D packaging. RDL line/space needs to be shrinking with the increasing of device density. We had been developed low temperature (LT) damascene process for the RDL formation in 3D interposer integration. The sample failed at thermal reliability test. High temperature (HT) RDL was developed and demonstrated after...
3D integration by TSV approach is a very hot topic now as an enabling technology for 3D wafer-level packaging and 3D IC. Re-distribution layer (RDL) process becomes more critical on high volume Cu (TSV) wafer because of Cu thermal stress effect. Fine pitch low temperature RDL is required in 3D packaging and 3D IC integration. We develop fine pitch (5μm space/5μm width) single and dual damascene processes...
3D integration by TSV approach is a very hot topic now as an enabling technology for 3D wafer-level packaging and 3D IC. Re-distribution layer (RDL) process becomes more critical on high volume Cu (TSV) wafer because of Cu thermal stress effect. Fine pitch low temperature RDL is required in 3D packaging and 3D IC integration. We develop fine pitch (5µm space/5µm width) single and dual damascene processes...
In this paper, the electrical characteristics, such as CV and IV, of TSV embedded in grounded Si are presented. The aim is to understand the interaction between TSV and silicon substrate. Process developments of TSV with diameter of 5μm and height of 5-10μm are discussed in terms of DRIE Si via etching, isolation deposition, Cu ECP and Cu CMP.
Limited battery power for wireless devices demands improvement in power efficiency while enhancing system performance. Traditional semiconductor scaling faces challenges to meet this requirement. 3D integration of multiple chips using through silicon via (TSV) is one of the technologies that can extend the performance scaling trend. However, the semiconductor industry will need to overcome many technology...
One of challenge for the 3D integration by the TSV approach is the electroplating. Electroplating quality and time are important parameters for TSV cost and application. Solid Cu filling TSV (Through Si Via) with via diameter 20 μm and 65μm depth is achieved by the DC (directly current) electroplating within 40 minutes on 8 inch wafer.
The 3 D interconnect technology with Thru Silicon Via (TSV) have gained tremendous advancement in recent years. Final adoption of TSV technologies requires a robust and cost competitive TSV processes. Sidewall plated TSV with polymer filling can reduce half of total process steps from TSV copper (Cu) seed deposition to front-via1 expose. TSV plating time can be reduced ~ 60% for sidewall plated TSV...
In the current 3D integration technology, the control of wafer warp is needed to ensure uniform photolithography, good bonding areas and other major processes that requires flat wafer surface. In this paper, we found out that the wafer warpage was increased with increasing TSV density. The highest wafer warpage was observed after Cu annealing base on step by step warpage monitor. Wafer warpage reduction...
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