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Molybdenum disulfide (MoS2), a member of the transition metal dichalcogenide (TMD) family, is a 2D semiconductor with a direct bandgap of ∼1.8 eV for single layers. Its bandgap allows for high Ion/Ioff metal-oxide semiconducting field-effect transistors (FETs). More relevant for radio frequency (RF) wireless applications, theoretical studies predict MoS2 to have saturation velocities, Vsat > 3×10...
7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are...
Recently long-channel PMOS transistors are being used in delay circuits to increase delay time. Negative Bias Temperature Instability (NBTI) has channel length dependency which shows that long-channel devices degrade more than short channel devices. We suggest a source underlap structure with short channel transistor to solve this problem. We confirmed the short-channel device with underlap structure...
Gate oxide and interface trap charges are critical parameters for device reliability and their generation and recovery are investigated under AC and DC oxide field stress on n-channel MOSFETs by C-V, I-V, and CP measurements. The interface traps generation is the same under both DC and AC stress but oxide charge trap generation is higher at AC stress than DC stress. The oxide charge and interface...
We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46 mV/dec and high ION/IOFF ratio (~108) and the experiment was successfully repeated after two months. Its superior operation is explained...
A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS Vfb and high pMOS...
A new and accurate approach to gate oxide reliability measurements for the determination of the gate oxide quality and lifetime estimation on MOSFET is presented. An accurate gate oxide thickness calculation by gate current provides oxide thickness variations better than conventional CV measurement. A gate oxide quality by gate current analysis is well correlated to the time dependent dielectric breakdown...
We have studied key parameters for controlling threshold voltage (Vth) variation and strain maintenance of gate first SiGe channel pMOSFETs. By overcoming 1) Ge diffusion and 2) strain relaxation during source/drain activation, we for the first time demonstrate high Ge% (50%) SiGe channel with millisecond flash anneal. Optimizing the thermal budget with millisecond anneal keeps the Vth variation same...
To make the revelation of ubiquity true different kind of network's integration is going on and this assimilation makes service discovery more challenging because different types of service discovery have been develop for the particular network. A Context-Aware Service Discovery for these amalgam networks is different from usual, especially when we talk about 6LoWPANs functioning with IP Networks,...
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs...
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics...
In this paper, we present a novel electrostatic discharge (ESD) protection device which is, against the catastrophic ESD attack, activated as either a reverse-biased punchthrough bipolar junction transistor (BJT) or a forward-biased diode, depending on the polarity of the input pulse. Experimental data show that the new device is more efficient and area-effective than any other conventional one. It...
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